SN54HCT374, SN74HCT374
OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS
WITH 3 STATE OUTPUTS
SCLS005D 鈭?MARCH 1984 鈭?REVISED AUGUST 2003
D
Operating Voltage Range of 4.5 V to 5.5 V
D
High-Current 3-State True Outputs Can
D
D
D
D
D
D
D
Drive Up To 15 LSTTL Loads
Low Power Consumption, 80-碌A(chǔ) Max I
CC
Typical t
pd
= 22 ns
鹵6-mA
Output Drive at 5 V
Low Input Current of 1
碌A(chǔ)
Max
Inputs Are TTL-Voltage Compatible
Eight D-Type Flip-Flops in a Single Package
Full Parallel Access for Loading
SN54HCT374 . . . J OR W PACKAGE
SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the 鈥橦CT374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54HCT374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
8Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8D
7D
7Q
6Q
6D
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TA
PDIP 鈭?N
SOIC 鈭?DW
SOP 鈭?NS
鈭?0擄C to 85擄C
SSOP 鈭?DB
PACKAGE鈥?/div>
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
TSSOP 鈭?PW
CDIP 鈭?J
鈭?5 C 125擄C
鈭?5擄C to 125 C
CFP 鈭?W
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
ORDERABLE
PART NUMBER
SN74HCT374N
SN74HCT374DW
SN74HCT374DWR
SN74HCT374NSR
SN74HCT374DBR
SN74HCT374PW
SN74HCT374PWR
SN74HCT374PWT
SNJ54HCT374J
SNJ54HCT374W
SNJ54HCT374J
SNJ54HCT374W
HT374
HCT374
HCT374
HT374
TOP-SIDE
MARKING
SN74HCT374N
LCCC 鈭?FK
Tube of 55
SNJ54HCT374FK
SNJ54HCT374FK
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
1
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