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JM38510/37204B2A Datasheet

  • JM38510/37204B2A

  • OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

  • 21頁

  • TI

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SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS167C 鈥?APRIL 1982 鈥?REVISED NOVEMBER 1999
D
D
D
D
D-Type Flip-Flops in a Single Package With
3-State Bus Driving True Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) DIPs
SN54ALS374A, SN54AS374 . . . J PACKAGE
SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE
(TOP VIEW)
description
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
driving
highly
capacitive
or
relatively
low-impedance loads. They are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
On the positive transition of the clock (CLK) input,
the Q outputs are set to the logic levels set up at
the data (D) inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ALS374A, SN54AS374 . . . FK PACKAGE
(TOP VIEW)
2D
2Q
3Q
3D
4D
3
4
5
6
7
8
2 1 20 19
18
17
16
15
OE
V
CC
8Q
8D
7D
7Q
6Q
6D
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range
of 鈥?5擄C to 125擄C. The SN74ALS374A and SN74AS374 are characterized for operation from 0擄C to 70擄C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE
L
L
L
H
CLK
鈫?/div>
鈫?/div>
H or L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
1D
1Q
14
9 10 11 12 13
1

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