鈥?/div>
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
SN54F74 . . . J PACKAGE
SN74F74 . . . D OR N PACKAGE
(TOP VIEW)
description
These devices contain two independent positive-
edge-triggered D-type flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets
the outputs regardless of the levels of the other
inputs. When PRE and CLR are inactive (high),
data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not
directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the
D input may be changed without affecting the
levels at the outputs.
The SN54F74 is characterized for operation over
the full military temperature range of 鈥?55擄C to
125擄C. The SN74F74 is characterized for
operation from 0擄C to 70擄C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
鈫?/div>
鈫?/div>
L
D
X
X
X
H
L
X
OUTPUTS
Q
H
L
H鈥?/div>
H
L
Q0
Q
L
H
H鈥?/div>
L
H
Q0
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54F74 . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1D
1CLR
NC
V
CC
2CLR
2D
NC
2CLK
NC
2PRE
NC 鈥?No internal connection
Copyright
漏
1993, Texas Instruments Incorporated
鈥?The output levels are not guaranteed to meet the
minimum levels for VOH. Furthermore, this
configuration is nonstable; that is, it will not persist
when PRE or CLR returns to its inactive (high)
level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
2鈥?
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