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JLC1563/D Datasheet

  • JLC1563/D

  • I2C Bus Transceiver

  • 12頁

  • ETC

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JLC1563
I2C Bus Transceiver
JLC1563 is an I2C鈥揵us signal transceiver and 鈥渃onditioner鈥欌€?
Currently, systems complexity and I2C鈥揵us device types and
functionality are only increasing. As a result of I2C鈥揵us loading the
Clock line and Data line signals degrade. The JLC1563 I2C鈥揃us
Transceiver restores clean signals in the system leading to
improvements in system performance and reliability.
This device has two pins, SCL1 (Serial Clock Input) and SDA1
(Serial Data I/O), on the Master I2C鈥揵us side; and two pins, SCL2
(Serial Clock Output) and SDA2 (Serial Data I/O), on the Slave
I2C鈥揵us side.
Two reset pins, Reset1 and Reset2, drive separate internal
comparators and a system Power鈥揙n鈥揜eset function is supported.
Features
http://onsemi.com
HIGH鈥揚ERFORMANCE CMOS
LOW鈥揚OWER COMPLEMENTARY
MOS SILICON鈥揋ATE
MARKING
DIAGRAMS
8
PDIP鈥?
P SUFFIX
CASE 626
1
1
8
8
1
SOEIAJ鈥?
M SUFFIX
CASE 968
1
1563
ALYW
JLC1563P
AWL
YYWW
鈥?/div>
Low Power Dissipation
鈥?/div>
Two Pin Reset/Power鈥揙n鈥揜eset
鈥?/div>
Waveform Cleaning
8
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
Device
JLC1563P
JLC1563M
JLC1563ML1
Package
PDIP鈥?
SOEIAJ鈥?
SOEIAJ鈥?
Shipping
50 Units/Rail
See Note 1.
See Note 1.
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.
漏
Semiconductor Components Industries, LLC, 2000
1
June, 2000 鈥?Rev. 0
Publication Order Number:
JLC1563/D

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