The documentation and process conversion measures necessary to comply
with this document shall be completed by 9 October 2002.
INCH-POUND
MIL-PRF-19500/559E
9 July 2002
SUPERSEDING
MIL-PRF-19500/559D
10 August 1998
PERFORMANCE SPECIFICATION
SEMICONDUCTOR DEVICE, UNITIZED, NPN, SILICON, SWITCHING,
FOUR TRANSISTOR ARRAY TYPES 2N6989, 2N6989U, AND 2N6990,
JAN, JANTX, JANTXV, AND JANS
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, switching transistors in a
four independent chip array. Four levels of product assurance are provided for each device type as specified in
MIL-PRF-19500.
1.2 Physical dimensions. See figures 1, 2, 3, 4 (14 pin dual-in-line, 14 pin flat package), and figure 5 (20 pin
surface mount).
1.3 Maximum ratings. (1)
Type
P
T
T
A
= +25擄C (2)
W
*2N6989
2N6989U
*2N6990
*
2.0
1.0
1.0
V
CBO
(3)
V dc
75
75
75
V
EBO
(3)
V
CEO
(3)
I
C
(3)
T
OP
and T
STG
V dc
6
6
6
V dc
50
50
50
mA dc
800
800
800
擄C
-65 to +200
-65 to +200
-65 to +200
(1) Maximum voltage between transistors shall be
鈮?/div>
500 V dc.
(2) Derate linearly 11.43 mW/擄C above T
A
= +25擄C for 2N6989 and 2N6989U. Derate linearly 5.71 mW/擄C
above T
A
= +25擄C for 2N6990. Ratings apply to total package.
(3) Ratings apply to each transistor in the array.
Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in
improving this document should be addressed to: Defense Supply Center, Columbus, ATTN: DSCC-VAC,
P.O. Box 3990, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD
Form 1426) appearing at the end of this document or by letter.
AMSC N/A
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
FSC 5961
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