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IZ4053B Datasheet

  • IZ4053B

  • Analog Multiplexer Demultiplexer

  • 8頁(yè)

  • ETC

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TECHNICAL DATA
IW4053B
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The IW4053B analog multiplexer/demultiplexer is digitally
controlled analog switches having low ON impedance and very low
OFF leakage current. Control of analog signals up to 20V peak-to-peak
can be achieved by digital signal amplitudes of 4.5 to 20V (if V
CC
- GND
= 3V, a V - V
EE
of up to 13 V can be controlled; for V
CC
- V
EE
level
CC
differences above 13V a V
CC
- GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full V
CC
-GND and V
CC
- V
EE
supply-voltage ranges,
independent of the logic state of the control signals. When a logic
鈥?鈥漣s present at the ENABLE input terminal all channels are off.
The IW4053B is a triple 2-channel multiplexer having three separate
digital control inputs, A, B, and C, and an enable input. Each control
input selects one of a pair of channels which are connected in a single-
pole double-throw configuration.
鈥?/div>
Operating Voltage Range: 3.0 to 18 V
鈥?/div>
Maximum input current of 1
碌A(chǔ)
at 18 V over full package-temperature
range; 100 nA at 18 V and 25擄C
鈥?/div>
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4053BN
Plastic DIP
IW4053BD
SOIC
IZ4053B
chip
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Triple Single-Pole, Double-Position
Plus Common Off
FUNCTION TABLE
Control Inputs
Enable
C
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
X
Select
B
L
L
H
H
L
L
H
H
X
A
L
H
L
H
L
H
L
H
X
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
None
X0
X1
X0
X1
X0
X1
X0
X1
ON
Channels
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
L
H
H = high level
L = low level
X = don鈥檛 care
INTEGRAL
1

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