鈩?/div>
T
C
= 25擄C
Maximum Ratings
500
500
鹵20
鹵30
12
48
13
18
5
140
-55 ... +150
150
-55 ... +150
300
3
V
V
V
V
A
A
A
mJ
V/ns
W
擄C
擄C
擄C
擄C
g
l
l
l
l
G
D
S
G = Gate,
S = Source
* Patent pending
Isolated back surface*
D = Drain,
Features
l
Silicon chip on Direct-Copper-Bond
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
Low drain to tab capacitance(<35pF)
Low R
DS (on)
HDMOS
TM
process
Rugged polysilicon gate cell structure
Unclamped Inductive Switching (UIS)
rated
Applications
l
Symbol
Test Conditions
Characteristic Values
(T
J
= 25擄C, unless otherwise specified)
min. typ. max.
500
2
4
鹵100
T
J
= 25擄C
T
J
= 125擄C
200
1
0.4
V
V
l
l
V
DSS
V
GS(th)
I
GSS
I
DSS
R
DS(on)
V
GS
= 0 V, I
D
= 250
碌A(chǔ)
V
DS
= V
GS
, I
D
= 2.5 mA
V
GS
=
鹵20
V
DC
, V
DS
= 0
V
DS
= 0.8 V
DSS
V
GS
= 0 V
V
GS
= 10 V, I
D
= I
T
Notes 1, 2
l
l
DC-DC converters
Batterychargers
Switched-mode and resonant-mode
power supplies
DC choppers
AC motor control
Advantages
nA
碌A(chǔ)
mA
鈩?/div>
l
l
l
l
Easy assembly: no screws or isolation
foils required
Space savings
High power density
Low collector capacitance to ground
(low EMI)
漏 2001 IXYS All rights reserved
98823 (05/01)
next