鈩?/div>
T
C
= 25擄C
26N50
24N50
26N50
24N50
26N50
24N50
Maximum Ratings
500
500
鹵20
鹵30
23
21
92
84
26
24
30
5
230
-55 ... +150
150
-55 ... +150
V
V
V
V
A
A
A
A
A
A
mJ
V/ns
W
擄C
擄C
擄C
擄C
V~
g
ISOPLUS 220
TM
G
D
S
Isolated back surface*
G = Gate
S = Source
D = Drain
* Patent pending
1.6 mm (0.062 in.) from case for 10 s
50/60 Hz, RMS
t = 1 minute leads-to-tab
300
2500
3
Features
l
Silicon chip on Direct-Copper-Bond
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
l
Low drain to tab capacitance(<35pF)
l
Low R
DS (on)
HDMOS
TM
process
l
Rugged polysilicon gate cell structure
l
Unclamped Inductive Switching (UIS)
rated
l
Fast intrinsic Rectifier
Applications
l
DC-DC converters
l
Battery chargers
l
Switched-mode and resonant-mode
power supplies
l
DC choppers
l
AC motor control
Advantages
l
Easy assembly: no screws, or isolation
foils required
l
Space savings
l
High power density
l
Low collector capacitance to ground
(low EMI)
Symbol
Test Conditions
Characteristic Values
(T
J
= 25擄C, unless otherwise specified)
min. typ. max.
500
2
4
鹵100
T
J
= 25擄C
T
J
= 125擄C
26N50
24N50
200
1
0.20
0.23
V
V
nA
碌A(chǔ)
mA
鈩?/div>
鈩?/div>
V
DSS
V
GS(th)
I
GSS
I
DSS
R
DS(on)
V
GS
= 0 V, I
D
= 250uA
V
DS
= V
GS
, I
D
= 4mA
V
GS
=
鹵20
V
DC
, V
DS
= 0
V
DS
= 0.8 V
DSS
V
GS
= 0 V
V
GS
= 10 V, I
D
= I
T
Notes 1 & 2
漏 2000 IXYS All rights reserved
98755 (10/00)
1
2
