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IXF6048 Datasheet

  • IXF6048

  • Telecommunication IC

  • 352頁

  • ETC

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IXF6048
51/155/622/2488 Mbit/s SONET/SDH Cell/Packet Interface
Datasheet
IXF6048 is a single-chip interface solution for the transport of ATM cells or HDLC frames over
SONET/SDH. IXF6048 can operate as a quad 51/155/622 Mbit/s or as a single 2488 Mbit/s
SONET/SDH processor. When configured in ATM UNI mode, it interfaces with an ATM layer
device using the industry standard UTOPIA interface (Levels 3/2/1). When configured in Packet
Over SONET mode, it transfers the PPP frames using a UTOPIA-enhanced interface, based on
the ATM industry standard UTOPIA, which supports the transfer of variable length frames.
Product Features
Applications
s
s
s
s
s
WAN and edge ATM switches
Layer 3 switches
Video and File Servers
Broadband Switching Systems
s
s
s
Features
s
s
Maps ATM cells or HDLC frames into one
STS-48c/STM-16c/STS-48/STM-16/STM-
4 or four STS-12c/STM-4c/STS-3c/STM-
1/STS-1 SONET/SDH signals.
In POS mode, each channel performs SPE
scrambling (1 + X
43
), HDLC processing,
and offers a UTOPIA-type FIFO-based
POS interface.
s
s
s
Supports the UTOPIA Level 3 (single 64-
bit, 32-bit, or quad 8-bit), Level 2 (single 8/
16-bit), and Level 1 (quad 8/16-bit)
interface modes.
Implements a GFC halt function (ITU I.150
and I.361).
Handles full J0/J1 trace identifier
processing.
SOH, POH and Alarm insertion/extraction
ports.
Hardware assistance for APS
implementation, via K1 and K2 bytes.
Provides a 16-bit microprocessor port.
One-second counters for B1/B2/B3, M1/G1
REI, etc.
600 TBGA package; -40擄C to +85擄C
operating conditions; low power, 3.3 V
operation, 5V tolerant I/O
Figure 1. Block Diagram
SOH / POH / Alarms Extraction Ports
channel #3
channel #2
channel #1
channel #0
IXF6048
Receive ATM/POS
Level 1/2/3 UTOPIA
Interface
Rx Line Interface
PECL 16-bit X 1
PECL 1-bit X 4
TTL 32-bit X 1
TTL 8-bit X 4
TTL 1-bit X 4
Receive
Serial to
Parallel
Interface
(RSPI)
SONET/
SDH
DEMUX
(non conca-
tenated
modes)
Receive
Regenera-tor
Section
Processor
(RRSP)
Receive
Multiplex
Section
Processor
(RMSP)
Receive
High-Order
Path
Processor
(RHPP)
Receive
POS Controller
(RPOSC)
Receive
ATM Cell Processor
(RACP)
32 or 2K
#3
32 or 2K
#2
32 or 2K
#1
256-cell (ATM)
16 KB (POS)
FIFO
#0
Rx UTOPIA
64-bit X 1
32-bit X 1
16-bit X 1
8-bit X 1
16-bit X 4
or
8-bit X 4
Remote Loop
Local Loop
Path FEBE
Line FEBE
GFC Halt
Section
Trace
Buffer
Path
Trace
Buffer
Tx Line Interface
PECL 16-bit X 1
PECL 1-bit X 4
TTL 32-bit X 1
TTL 8-bit X 4
TTL 1-bit X 4
Transmit
Parallel to
Serial
Interface
(TPSI)
SONET/
SDH
MUX
(non conca-
tenated
modes)
Transmit ATM/POS
Level 1/2/3 UTOPIA
Interface
Transmit
Regenera-tor
Section
Processor
(TRSP)
Transmit
Multiplex
Section
Processor
(TMSP)
Transmit
High-Order
Path
Processor
(THPP)
Transmit
ATM Cell Processor
(TACP)
Transmit
POS Controller
(TPOSC)
32 or 2K
#3
32 or 2K
#2
32 or 2K
#1
256-cell (ATM)
16 KB (POS)
FIFO
#0
Tx UTOPIA
64-bit X 1
32-bit X 1
16-bit X 1
8-bit X 1
16-bit X 4
or
8-bit X 4
JTAG
Interface
JTAG Test
Access Port
SOH / POH / Alarms Insertion Ports
Microprocessor Interface
16bit, Intel/Motorola selectable
(MPI)
碌P
lines
Order Number: 273644-001
November 2001

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