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IW4013BN Datasheet

  • IW4013BN

  • Dual D Flip-Flop High-Voltage Silicon-Gate CMOS

  • 180.85KB

  • 5頁

  • INTEGRAL

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TECHNICAL DATA
IW4013B
Dual D Flip-Flop
High-Voltage Silicon-Gate CMOS
The IW4013B consists of two identical, independent data-type flip-
flops. Each flip-flop has independent data, set, reset, and clock inputs
and Q and Q outputs. These devices can be used for shift register
applications, and, by connecting Q output to the data input, for counter
and toggle applications. The logic level present at the D input is
transferred to the Q output during the positive-going transition of the
clock pulse. Setting or resetting is independent of the clock and is
accomplished by a high level on the set or reset line, respectively.
鈥?/div>
Operating Voltage Range: 3.0 to 18 V
鈥?/div>
Maximum input current of 1
碌A
at 18 V over full package-
temperature range; 100 nA at 18 V and 25擄C
鈥?/div>
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4013BN Plastic
IW4013BD SOIC
T
A
= -55擄 to 125擄 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Clock Data Reset Set
L
H
X
X
PIN 14 =V
CC
PIN 7 = GND
X
X
X
X
X
L
L
L
H
L
H
L
L
L
L
H
H
Outputs
Q
L
H
Q
L
H
H
Q
H
L
Q
H
L
H
X = don鈥檛 care
19

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