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ISPPAC10-01SI Datasheet

  • ISPPAC10-01SI

  • In-System Programmable Analog Circuit

  • 413.13KB

  • 23頁

  • LATTICE   LATTICE

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ispPAC 10
廬
In-System Programmable Analog Circuit
Features
鈥?IN-SYSTEM PROGRAMMABLE (ISP鈩? ANALOG CIRCUIT
鈥?Four Instrument Amplifier Gain/Attenuation Stages
鈥?Signal Summation (Up to 4 Inputs)
鈥?Precision Active Filtering (10kHz to 100kHz)
鈥?No External Components Needed for Configuration
鈥?Non-Volatile E
2
CMOS
廬
Cells (10,000 Cycles)
鈥?IEEE 1149.1 JTAG Serial Port Programming
鈥?FOUR LINEAR ELEMENT BUILDING BLOCKS
鈥?Programmable Gain Range (0dB to 80dB)
鈥?Bandwidth of 550kHz (G=1), 330kHz (G=10)
鈥?Low Distortion (THD < -74dB max @ 10kHz)
鈥?Auto-Calibrated Input Offset Voltage
鈥?TRUE DIFFERENTIAL I/O (
鹵
3V RANGE)
鈥?High CMR (69dB) Instrument Amplifier Inputs
鈥?2.5V Common Mode Reference on Chip
鈥?Four Rail-to-Rail Voltage Outputs
鈥?28-PIN PLASTIC DIP OR SOIC PACKAGE
鈥?Single Supply 5V Operation
鈥?APPLICATIONS INCLUDE INTEGRATED:
鈥?Single +5V Supply Signal Conditioning
鈥?Active Filters, Gain Stages, Summing Blocks
鈥?Analog Front Ends, 12-Bit Data Acq. Systems
鈥?Sensor Signal Conditioning
Functional Block Diagram
OUT2+
OUT2鈥?/div>
IN2+
IN2鈥?/div>
TDI
TRST
VS
TDO
TCK
1
2
3
4
5
6
7
8
9
IA
IA
IA
IA
OA
OA
28 OUT1+
27 OUT1鈥?/div>
26 IN1+
IA
IA
25 IN1鈥?/div>
24 TEST
23 TEST
Configuration Memory
Analog Routing Pool
Reference & Auto-Calibration
22 VREF
OUT
21 GND
20 CAL
IA
IA
19 CMV
IN
18 IN3鈥?/div>
17 IN3+
16 OUT3鈥?/div>
TMS 10
IN4鈥?11
IN4+ 12
OUT4鈥?13
OUT4+ 14
Description
The ispPAC10 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E
2
CMOS technology.
Analog function modules, called PACblocks鈩? replace
traditional analog components such as op amps and
active filters, eliminating the need for most external
resistors and capacitors. With no requirement for exter-
nal configuration components, ispPAC10 expedites the
design process, simplifying prototype circuit implemen-
tation and change, while providing high performance and
integrated functionality.
Designers configure the ispPAC10 and verify its perfor-
mance using PAC-Designer
廬
, an easy-to-use, Microsoft
Windows
廬
compatible development tool. Device pro-
gramming is supported using PC parallel port I/O
operations. A library of configurations is included with basic
solutions and examples of advanced circuit techniques.
The ispPAC10 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-
System Programming capability enables programming,
verification and reconfiguration if desired, directly on the
printed circuit board.
OA
OA
15 OUT3+
Typical Application Diagram
5V
Vin
5V
12-Bit
Differential
Input ADC
Ain+
Ain-
Ref+
Ref-
ispPAC10
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
pac10_04
1

ISPPAC10-01SI 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡單可編程邏輯器件

  • ISPPA

  • 5 ns

  • 3 V to 3.6 V

  • + 85 C

  • - 40 C

  • SOIC-28

  • SMD/SMT

  • 27

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