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ISPMACH4ACPLDFAMILY Datasheet

  • ISPMACH4ACPLDFAMILY

  • High Performance E 2 CMOS In-System Programmable Logic

  • 62頁

  • LATTICE   LATTICE

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High Performance E
2
CMOS
廬
In-System Programmable Logic
FEATURES
x
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
ispMACH
鈩?/div>
4A CPLD Family
x
x
x
x
x
x
x
x
鈥?Excellent First-Time-Fit
TM
and re鏗乼 feature
鈥?SpeedLocking
TM
performance for guaranteed 鏗亁ed timing
鈥?Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
鈥?5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
鈥?182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
鈥?D/T registers and latches
鈥?Synchronous or asynchronous mode
鈥?Dedicated input registers
鈥?Programmable polarity
鈥?Reset/ preset swapping
Advanced capabilities for easy system integration
鈥?3.3-V & 5-V JEDEC-compliant operations
鈥?JTAG (IEEE 1149.1) compliant for boundary scan testing
鈥?3.3-V & 5-V JTAG in-system programming
鈥?PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
鈥?Safe for mixed supply voltage system designs
鈥?Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
鈥?Hot-socketing
鈥?Programmable security bit
鈥?Individual output slew rate control
Advanced E
2
CMOS process provides high-performance, cost-effective solutions
Supported by ispDesignEXPERT
TM
software for rapid logic development
鈥?Supports HDL design methodologies with results optimized for ispMACH 4A
鈥?Flexibility to adapt to user requirements
鈥?Software partnerships that ensure customer success
Lattice and third-party hardware programming support
鈥?LatticePRO
TM
software for in-system programmability support on PCs and automated test
equipment
鈥?Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
ISPM4A
Amendment/0
Rev:
D
Issue Date:
August 2000

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