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ISPLSI3448-90LB432 Datasheet

  • ISPLSI3448-90LB432

  • Electrically-Erasable Complex PLD

  • 174.00KB

  • 14頁(yè)

  • ETC

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ispLSI 3448
廬
In-System Programmable High Density PLD
Features
鈥?HIGH-DENSITY PROGRAMMABLE LOGIC
鈥?224 I/O
鈥?20000 PLD Gates
鈥?672 Registers
鈥?High Speed Global Interconnect
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?HIGH-PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 90 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 12 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?ispLSI FEATURES:
鈥?5V In-System Programmable (ISP鈩? Using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Debugging
鈥?100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
0139/3448
Functional Block Diagram
Boundary
Scan
Output Routing Pool (ORP)
J3
J2
J1
J0
...
Output Routing Pool (ORP)
H3
H2
H1
H0
Output Routing Pool (ORP)
K0
D Q
G3
K1
K2
D Q
OR
Array
D Q
G2
G1
AND Array
D Q
K3
D Q
Twin
GLB
G0
OR
Array
D Q
D Q
Output Routing Pool (ORP)
N0
D3
N1
N2
D2
Global Routing Pool
(GRP)
D1
N3
D0
A0
A1
A2
A3
C0
C1
C2
C3
Output Routing Pool (ORP)
...
Output Routing Pool (ORP)
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Enhanced Pin Locking Capability
鈥?Five Dedicated Clock Inputs
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to Mini-
mize Switching Noise
鈥?Flexible I/O Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Description
The ispLSI 3448 is a High-Density Programmable Logic
Device containing 672 Registers, 224 Universal I/Os, five
Dedicated Clock Inputs, 14 Output Routing Pools (ORP)
and a Global Routing Pool (GRP) which allows complete
inter-connectivity between all of these elements. The
ispLSI 3448 features 5V in-system programmability and
in-system diagnostic capabilities. The ispLSI 3448 offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 3448 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3.
There are a total of 56 of these Twin GLBs in the ispLSI
3448 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 2000
3448_06
1
Output Routing Pool (ORP)
D Q
Output Routing Pool (ORP)
...
...

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