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ISPLSI3160-125LM Datasheet

  • ISPLSI3160-125LM

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ispLSI 3160
廬
In-System Programmable High Density PLD
Features
鈥?HIGH-DENSITY PROGRAMMABLE LOGIC
鈥?160 I/O Pins
鈥?7000 PLD Gates
鈥?320 Registers
鈥?High Speed Global Interconnect
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?HIGH PERFORMANCE E CMOS TECHNOLOGY
鈥?/div>
f
max
= 125 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 7.5 ns Propagation Delay
鈥?TTL Compatible Inputs and Outputs
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?IN-SYSTEM PROGRAMMABLE
鈥?5V In-System Programmability (ISP鈩? Using
Lattice ISP or Boundary Scan Test (IEEE 1149.1)
Protocol
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Debugging
鈥?100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
鈥?OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
鈥?Complete Programmable Device Can Combine Glue
Logic and Structured Designs
鈥?Five Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control to Mini-
mize Switching Noise
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
2
廬
Functional Block Diagram
ORP
E3
E2
E1
ORP
E0
ISP and
Boundary
Scan TAP
A0
D Q
D3
ORP
ORP
A1
OR
Array
AND Array
D Q
D2
D Q
D Q
A2
ORP
D Q
Twin
GLB
D1
ORP
A3
OR
Array
D Q
D0
D Q
D Q
B0
ORP
C3
ORP
B1
Global Routing Pool
(GRP)
C2
B2
ORP
C1
ORP
B3
C0
Description
The ispLSI 3160 is a High-Density Programmable Logic
Devices containing 320 Registers, 160 Universal I/O
pins, five Dedicated Clock Input Pins, five Output Routing
Pools (ORP) and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3160 features 5V in-system pro-
grammability and in-system diagnostic capabilities. The
ispLSI 3160 offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3160 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...E3.
There are a total of 20 of these Twin GLBs in the ispLSI
3160 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 1999
3160_08
1

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