鈥?Reprogram Soldered Devices for Faster Prototyping
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
鈥?Enhanced Pin Locking Capability
鈥?Three Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
Input Bus
廬
Functional Block Diagram
Output Routing Pool (ORP)
A0
Output Routing Pool (ORP)
鈥?/div>
Input Bus
A2
GLB
Logic
Array
D Q
D Q
B1
D
D Q
鈥?/div>
A3
A4
A5
B0
A7
N
EW
A6
Output Routing Pool (ORP)
Input Bus
鈥?/div>
0139A/2064V
鈥?/div>
SI
2
06
4V
E
U
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
SE
is
pL
FO
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1鈥7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
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