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ISPLSI2032VL Datasheet

  • ISPLSI2032VL

  • Lattice Semiconductor [2.5V In-System Programmable SuperFAS...

  • 158.14KB

  • LATTICE   LATTICE

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ispLSI 2032VL
2.5V In-System Programmable
SuperFAST鈩?High Density PLD
Features
鈥?SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
鈥?1000 PLD Gates
鈥?32 I/O Pins, Two Dedicated Inputs
鈥?32 Registers
鈥?High Speed Global Interconnect
鈥?Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
鈥?Small Logic Block Size for Random Logic
鈥?100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V and 2032VE Devices
鈥?2.5V LOW VOLTAGE 2032 ARCHITECTURE
鈥?Interfaces With Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
鈥?45 mA Typical Active Current
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?/div>
f
max
= 180 MHz Maximum Operating Frequency
鈥?/div>
t
pd
= 5.0 ns Propagation Delay
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile
鈥?100% Tested at Time of Manufacture
鈥?Unused Product Term Shutdown Saves Power
鈥?IN-SYSTEM PROGRAMMABLE
鈥?2.5V In-System Programmability (ISP鈩? Using
Boundary Scan Test Access Port (TAP)
鈥?Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
鈥?Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
鈥?Reprogram Soldered Devices for Faster Prototyping
鈥?100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
鈥?THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
鈥?Enhanced Pin Locking Capability
鈥?Three Dedicated Clock Input Pins
鈥?Synchronous and Asynchronous Clocks
鈥?Programmable Output Slew Rate Control
鈥?Flexible Pin Placement
鈥?Optimized Global Routing Pool Provides Global
Interconnectivity
鈥?ispDesignEXPERT鈩?鈥?LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
鈥?Superior Quality of Results
鈥?Tightly Integrated with Leading CAE Vendor Tools
鈥?Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER鈩?/div>
鈥?PC and UNIX Platforms
廬
Functional Block Diagram
A0
Output Routing Pool (ORP)
Input Bus
A2
GLB
Logic
Array
D Q
D Q
A5
D Q
A3
A4
0139Bisp/2000
Description
The ispLSI 2032VL is a High Density Programmable
Logic Device containing 32 Registers, 32 Universal I/O
pins, two Dedicated Input Pins, three Dedicated Clock
Input Pins, one dedicated Global OE input pin and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032VL features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VL offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 2032VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright 漏 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2032vl_02
1
Input Bus
A1
D Q
A6
Output Routing Pool (ORP)
Global Routing Pool
(GRP)
A7

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