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ISPGDX240VA-10B388I Datasheet

  • ISPGDX240VA-10B388I

  • Telecomm/Datacomm

  • 23頁

  • ETC

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ispGDX 240VA
In-System Programmable
3.3V Generic Digital Crosspoint
Features
鈥?IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
鈥?240 I/O, 鈥淎ny Input to Any Output鈥?Routing
鈥?Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
鈥?Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
鈥?Space-Saving Fine Pitch BGA Packaging
鈥?Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?3.3V Core Power Supply
鈥?4.5ns Input-to-Output/4.0ns Clock-to-Output Delay
鈥?200MHz Maximum Clock Frequency
鈥?TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)
鈥?Low-Power: 20.0mA Quiescent Icc
鈥?24mA I
OL
Drive with Programmable Slew Rate
Control Option
鈥?PCI Compatible Drive Capability
鈥?Schmitt Trigger Inputs for Noise Immunity
鈥?Electrically Erasable and Reprogrammable
鈥?Non-Volatile E
2
CMOS Technology
鈥?ispGDXVA OFFERS THE FOLLOWING ADVANTAGES
鈥?3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
鈥?Change Interconnects in Seconds
鈥?FLEXIBLE ARCHITECTURE
鈥?Combinatorial/Latched/Registered Inputs or Outputs
鈥?Individual I/O Tri-state Control with Polarity Control
鈥?Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins (60)
鈥?Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns)
鈥?Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
鈥?Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
鈥?Outputs Tri-state During Power-up (鈥淟ive Insertion鈥?/div>
Friendly)
廬
Functional Block Diagram
I/O Pins D
ISP
Control
I/O Pins C
I/O Pins A
I/O
Cells
Global Routing
Pool
(GRP)
I/O
Cells
Boundary
Scan
Control
I/O Pins B
Description
The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
鈥?Multi-Port Multiprocessor Interfaces
鈥?Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
鈥?Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
鈥?Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX240VA device features fast operation, with
input-to-output signal delays (Tpd) of 4.5ns and clock-to-
output delays of 4.0ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
Copyright 漏 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 2002
gdx240va_05
1

ISPGDX240VA-10B388I 產(chǎn)品屬性

  • Lattice

  • 240 x 240

  • PLCC-28

  • TTL

  • TTL

  • 3.6 V

  • 3 V

  • + 85 C

  • - 40 C

  • Digital Crosspoint

  • Tray

  • SMD/SMT

  • 1

  • 3.3 V

  • 300

  • Single

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