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ISPGAL22V10C-7LK Datasheet

  • ISPGAL22V10C-7LK

  • Electrically-Erasable PLD

  • 14頁(yè)

  • ETC

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上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

ispGAL22V10
In-System Programmable E
2
CMOS PLD
Generic Array Logic鈩?/div>
Features
鈥?IN-SYSTEM PROGRAMMABLE鈩?(5-V ONLY)
鈥?4-Wire Serial Programming Interface
鈥?Minimum 10,000 Program/Erase Cycles
鈥?Built-in Pull-Down on SDI Pin Eliminates Discrete
Resistor on Board (ispGAL22V10C Only)
鈥?HIGH PERFORMANCE E
2
CMOS
廬
TECHNOLOGY
鈥?7.5 ns Maximum Propagation Delay
鈥?Fmax = 111 MHz
鈥?5 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
鈥?COMPATIBLE WITH STANDARD 22V10 DEVICES
鈥?Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and CMOS 22V10 Devices
鈥?E
2
CELL TECHNOLOGY
鈥?In-System Programmable Logic
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?TEN OUTPUT LOGIC MACROCELLS
鈥?Maximum Flexibility for Complex Logic Designs
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Software-Driven Hardware Configuration
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
I
12
OLMC
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I
14
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I
I/O/Q
12
I
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
SDO
SDI
MODE
SCLK
PROGRAMMING
LOGIC
8
OLMC
I/O/Q
PRESET
Description
The ispGAL22V10, at 7.5ns maximum propagation delay time,
combines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the industry's first in-
system programmable 22V10 device. E
2
technology offers high
speed (<100ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by al-
lowing the Output Logic Macrocell (OLMC) to be configured by the
user. The ispGAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices. The stan-
dard PLCC package provides the same functional pinout as the
standard 22V10 PLCC package with No-Connect pins being used
for the ISP interface signals.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
SCLK
I/O/Q
I/O/Q
I
I
Vcc
SSOP
4
I
I
I
MODE
I
I
I
11 12
7
5
2
28
26
25
I/O/Q
I/O/Q
SCLK
I/CLK
I
I
I
I
I
MODE
I
I
I
I
I
GND
1
28
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
SDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
SDI
ispGAL22V10
Top View
23
I/O/Q
SDO
7
ispGAL
22V10
22
Top View
9
21
I/O/Q
I/O/Q
14
16
18 19
I/O/Q
14
15
I
I
GND
SDI
I
Copyright 漏 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
isp22v10_02
1

ISPGAL22V10C-7LK 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡(jiǎn)單可編程邏輯器件

  • ispGAL

  • 10

  • 111 MHz

  • 10

  • 7.5 ns

  • 5 V

  • 140 mA

  • + 75 C

  • 0 C

  • SSOP-28

  • SMD/SMT

  • Tube

  • 470

  • 5.25 V

  • 4.75 V

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