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ISPGAL22LV10-10LJ Datasheet

  • ISPGAL22LV10-10LJ

  • Electrically-Erasable PLD

  • 14頁(yè)

  • ETC

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ispGAL
廬
22LV10
In-System Programmable Low Voltage
E
2
CMOS
廬
PLD Generic Array Logic鈩?/div>
Features
鈥?IN-SYSTEM PROGRAMMABLE
鈥?IEEE 1149.1 Standard TAP Controller Port
Programming
鈥?4-Wire Serial Programming Interface
鈥?Minimum 10,000 Program/Erase Cycles
鈥?HIGH PERFORMANCE E CMOS TECHNOLOGY
鈥?4 ns Maximum Propagation Delay
鈥?Fmax = 250 MHz
鈥?3 ns Maximum from Clock Input to Data Output
鈥?UltraMOS
廬
Advanced CMOS Technology
鈥?3.3V LOW VOLTAGE 22V10 ARCHITECTURE
鈥?JEDEC-Compatible 3.3V Interface Standard
鈥?5V Tolerant Inputs and I/O
鈥?I/O Interfaces with Standard 5V TTL Devices
鈥?ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
鈥?COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES
鈥?Function/Fuse-Map Compatible with 22LV10/22V10
Devices
鈥?Parametric Compatible with 22LV10
鈥?E
2
CELL TECHNOLOGY
鈥?In-System Programmable Logic
鈥?100% Tested/100% Yields
鈥?High Speed Electrical Erasure (<100ms)
鈥?20 Year Data Retention
鈥?APPLICATIONS INCLUDE:
鈥?DMA Control
鈥?State Machine Control
鈥?High Speed Graphics Processing
鈥?Software-Driven Hardware Configuration
鈥?ELECTRONIC SIGNATURE FOR IDENTIFICATION
2
廬
Functional Block Diagram
Spe
Gra ed
de
4ns
New
I/CLK
RESET
8
OLMC
I/O/Q
I
10
I
12
OLMC
I/O/Q
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
I
14
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I
I/O/Q
12
I
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
TDO
TDI
TMS
TCK
PROGRAMMING
LOGIC
8
OLMC
I/O/Q
PRESET
Description
The ispGAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. The
ispGAL22LV10 can interface with both 3.3V and 5V signal levels.
The ispGAL22LV10 is fully function/fuse map compatible with the
GAL
廬
22LV10 and GAL22V10. Further, the ispGAL22LV10 is para-
metric compatible with the GAL22LV10. The ispGAL22LV10 also
shares the same 28-pin PLCC package pin-out as the GAL22LV10.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/O/Q
I/O/Q
TCK
Vcc
I
I
SSOP
4
I
I
I
TMS
I
I
I
11
12
9
7
5
2
28
26
25
I/O/Q
I/O/Q
ispGAL22LV10
Top View
23
I/O/Q
TDO
21
I/O/Q
I/O/Q
14
16
19
18
I/O/Q
TCK
I/CLK
I
I
I
I
I
TMS
I
I
I
I
I
GND
1
28
7
ispGAL
22LV10
22
Top View
14
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
TDI
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
I/O/Q
GND
TDI
I
I
I
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
December 1999
isp22lv_06
1

ISPGAL22LV10-10LJ 產(chǎn)品屬性

  • Lattice

  • SPLD - 簡(jiǎn)單可編程邏輯器件

  • ispGAL

  • 10

  • 111 MHz

  • 10

  • 10 ns

  • 3.3 V

  • 130 mA

  • + 75 C

  • 0 C

  • PLCC-28

  • SMD/SMT

  • Tube

  • 370

  • 3.6 V

  • 3 V

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