The ispGAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
2
CMOS process, which combines CMOS with
Electrically Erasable (E
2
) floating gate technology. The
ispGAL22LV10 can interface with both 3.3V and 5V signal levels.
The ispGAL22LV10 is fully function/fuse map compatible with the
GAL
廬
22LV10 and GAL22V10. Further, the ispGAL22LV10 is para-
metric compatible with the GAL22LV10. The ispGAL22LV10 also
shares the same 28-pin PLCC package pin-out as the GAL22LV10.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I/CLK
I/O/Q
I/O/Q
TCK
Vcc
I
I
SSOP
4
I
I
I
TMS
I
I
I
11
12
9
7
5
2
28
26
25
I/O/Q
I/O/Q
ispGAL22LV10
Top View
23
I/O/Q
TDO
21
I/O/Q
I/O/Q
14
16
19
18
I/O/Q
TCK
I/CLK
I
I
I
I
I
TMS
I
I
I
I
I
GND
1
28
7
ispGAL
22LV10
22
Top View
14
15
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
TDI
Copyright 漏 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
1
2
3
4
5
6
7
8
9
10
11
12
13
14
