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ISP2200/33 Datasheet

  • ISP2200/33

  • Controller Miscellaneous - Datasheet Reference

  • 8頁

  • ETC

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QLogic Corporation
ISP2200 Intelligent Fibre Channel Processors
Data Sheet
Features
s
Product Description
The ISP2200 is a single-chip, highly integrated, bus
master, Fibre Channel processor that targets storage,
clustering, and networking applications. This chip
connects the PCI bus to a Fibre Channel loop or to a
point-to-point Fibre Channel port.
The ISP2200 is pin compatible with the ISP2100A.
The ISP2200 is a fully autonomous device, capable of
managing multiple I/O operations and associated data
transfers from start to 鏗乶ish without host intervention.
The ISP2200 provides power management support in
accordance with the
PCI Bus Power Management Interface
Speci鏗乧ation.
The ISP2200 block diagram is illustrated in
鏗乬ure 1.
Available in two versions:
脤
66-MHz, 64-bit PCI host bus interface
(ISP2200/66)
脤
33-MHz, 64-bit PCI host bus interface
(ISP2200/33)
Compliance with
PCI Local Bus Speci鏗乧ation
revision 2.1
Supports full-duplex communications in all Fibre
Channel topologies
Compliance with ANSI SCSI standards for class 2
and class 3 service:
脤
Fibre Channel Arbitrated Loop (FC-AL-2)
working draft, rev 5.7, August 22, 1997
脤
Fibre Channel Fabric Loop Attachment
(FC-FLA)
working draft, rev 2.7, August 12,
1997
脤
Fibre Channel Private Loop SCSI Direct Attach
(FC-PLDA)
working draft, rev 2.0, August 4,
1997
Supports Fibre Channel protocol SCSI (FCP-SCSI)
and Fibre Channel IP protocols
Compliance with
PCI Bus Power Management
Interface Speci鏗乧ation
Revision 1.0 (PC97)
Supports up to 200 Mbytes/sec sustained Fibre
Channel data transfer rate
Initiator, initiator/target, and target modes
Onboard, enhanced RISC processor to execute
operations at the I/O control-block (IOCB) level
from the host memory
Onboard gigabit serial transceivers
Supports external transceivers with a
10-bit interface
Supports PCI dual-address cycle (64-bit
addressing) and cache commands
No host intervention required to execute SCSI and
IP operations from start to 鏗乶ish
Simultaneous, multiple logical threads
Full duplex frame buffer architecture
Supports JTAG boundary scan
Supports multi-ID aliasing
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83220-580-00 B
ISP2200
1

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