QLogic Corporation
ISP1280 Intelligent, Dual SCSI Processor
Data Sheet
Features
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Compliance with ANSI X3T10/1142D
SCSI
Parallel Interconnect-2 (SPI-2)
draft
64-bit PCI host bus interface, compliant with
PCI
Local Bus Speci鏗乧ation
rev 2.1
Compliance with
PCI Bus Power Management
Interface Speci鏗乧ation
Revision 1.0 (PC98)
Two concurrently operating wide, Ultra2 SCSI
channels
Up to 80 Mbytes/sec parallel SCSI transfer rates
Supports single-ended, low voltage differential
(LVD) SCSI and high voltage differential (HVD)
SCSI
SCSI initiator and target modes of operation
Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
Supports PCI dual-address cycle (64-bit
addressing)
No host intervention required to execute SCSI
operations from start to 鏗乶ish
Simultaneous, multiple logical threads
JTAG boundary scan support
Product Description
The ISP1280 adds dual channel, Ultra2 (Fast-40) SCSI
support to the expanding functionality of the ISP. The
product is a single-chip, highly integrated bus master,
dual-channel SCSI I/O processor for SCSI initiator and
target applications. This device interfaces the PCI bus to
two Ultra2 (Fast-40) SCSI buses and contains an onboard
RISC processor. The product is a fully autonomous device,
capable of managing multiple I/O operations and
associated data transfers from start to 鏗乶ish without host
intervention. The ISP1280 provides power management
feature support in accordance with the
PCI Bus Power
Management Interface Speci鏗乧ation.
The ISP1280 is
host-software compatible with the QLogic ISP1240 chip.
The ISP1280 block diagram is illustrated in 鏗乬ure 1.
ISP1280
HOST MEMORY
PCI INTERFACE
DMA BUS 0
512-BYTE
DATA FIFO
64-BIT
PCI
BUS
SXP 0
SCSI INTERFACE
FIFO
WCS AND
BUFFERS
SEQUENCERS
CTRL REGS
ULTRA, WIDE
SCSI BUS 0
HOST SOFTWARE
DRIVER
IOCBS
REQUEST
QUEUE
512-BYTE
DATA FIFO
128-BYTE
COMMAND FIFO
DMA
CONTROL
RESPONSE
QUEUE
MAILBOX
REGISTERS
CTRL/CONFIG
REGISTERS
DMA BUS 1
RISC I/O BUS
SXP 1
FIFO
WCS AND
BUFFERS
SEQUENCERS
CTRL REGS
ULTRA, WIDE
SCSI BUS 1
RISC
REGISTER
FILE
BOOT
CODE
MEMORY
INTERFACE
ALU
ADDRESS 16
NVRAM
FLASH
BIOS
DATA 16
EXTERNAL
CODE/DATA
MEMORY
Figure 1. ISP1280 Block Diagram
83280-580-00 B
ISP1280
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