QLogic Corporation
ISP1080 Intelligent SCSI Processor
Data Sheet
Features
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Compliance with draft ANSI X3.302-199x Ultra2
SCSI (SPI-2) standard
64-bit PCI host bus interface, compliant with
PCI
Local Bus Speci鏗乧ation
rev 2.1
Compliance with
PCI Bus Power Management
Interface Speci鏗乧ation
Revision 1.0 (PC97)
Up to 80 Mbytes/sec parallel SCSI transfer rates
SCSI initiator and target modes of operation
Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
Supports PCI dual-address cycle (64-bit
addressing)
No host intervention required to execute SCSI
operations from start to 鏗乶ish
Simultaneous, multiple logical threads
JTAG boundary scan support
Product Description
The ISP1080 adds Ultra2 (Fast-40) SCSI support to the
expanding functionality of the ISP. The product is a
single-chip, highly integrated bus master, SCSI I/O
processor for SCSI initiator and target applications. This
device interfaces the PCI bus to an ANSI Ultra2 (Fast-40)
SCSI bus and contains an onboard RISC processor. The
product is a fully autonomous device, capable of managing
multiple I/O operations and associated data transfers from
start to 鏗乶ish without host intervention. The ISP1080
provides power management feature support in accordance
with the
PCI Bus Power Management Interface
Speci鏗乧ation.
The ISP1080 is host-software compatible
with the QLogic ISP1020 and ISP1040 chips. The ISP1080
block diagram is illustrated in 鏗乬ure 1.
ISP1080
HOST MEMORY
HOST SOFTWARE
DRIVER
IOCBS
REQUEST
QUEUE
64-BIT
PCI
BUS
PCI INTERFACE
DMA BUS
512-BYTE
DATA FIFO
SXP SCSI ENGINE
FIFO
WCS
128-BYTE
COMMAND FIFO
RISC I/O DATA BUS
COMMAND
BUFFER
MESSAGE
BUFFER
DMA
CONTROL
RISC
REGISTER
FILE
BOOT
CODE
MEMORY
INTERFACE
SXP CODE
Ultra2 LVD
WIDE SCSI BUS
MAILBOX
REGISTERS
ALU
SEQUENCERS
CONTROL
REGISTERS
RESPONSE
QUEUE
CTRL/CONFIG
REGISTERS
16-BIT ADDRESS
NVRAM
FLASH
BIOS
16-BIT DATA
EXTERNAL
CODE/DATA
MEMORY
Figure 1. ISP1080 Block Diagram
83180-580-00 B
PRELIMINARY
ISP1080
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