QLogic Corporation
ISP10160A/33 Intelligent SCSI Processor
Data Sheet
Features
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Supports a 33-MHz, 64-bit PCI host bus interface
with a 264 MB/sec maximum PCI transfer rate.
Compliance with
PCI Local Bus Specification
rev 2.1
Compliance with ANSI draft T10/1302D
SCSI-3
Parallel Interface
(SPI-3)
Supports Ultra3 (Fast-80) SCSI
SCSI feature set: dual transition, CRC, domain
validation
Compliance with
PCI Bus Power Management
Interface Specification
revision 1.0 (PC98)
Supports one wide Ultra3 (Fast-80) SCSI channel
Up to 160 Mbytes/sec parallel SCSI transfer rate
Supports single-ended, low voltage differential
(LVD) SCSI
SCSI initiator and target modes of operation
On-board RISC processor to execute operations at
the I/O control-block level from the host memory
Supports PCI dual-address cycle (64-bit
addressing)
No host intervention required to execute SCSI
operations from start to finish
Simultaneous, multiple logical threads
JTAG boundary scan support
Product Description
The ISP10160A supports single channel, Ultra3 SCSI
functionality and is pin compatible with QLogic鈥檚
ISP12160A Ultra3 SCSI processor, as well as QLogic鈥檚
ISP1280 dual channel SCSI processor. The ISP10160A is
a single-chip, highly integrated bus master, single-channel
SCSI I/O processor for SCSI initiator and target
applications. This device interfaces the PCI bus to an Ultra3
SCSI bus and contains an on-board RISC processor. The
product is a fully autonomous device, capable of managing
multiple I/O operations and associated data transfers from
start to finish without host intervention. The ISP10160A
provides power management feature support in accordance
with the
PCI Bus Power Management Interface
Specification.
The ISP10160A block diagram is illustrated
in figure 1.
ISP10160A
PCI INTERFACE
HOST SOFTWARE
DRIVER
IOCBS
REQUEST
QUEUE
RISC I/O BUS
CTRL REGS
64-BIT
PCI
BUS
DMA BUS
1K-BYTE
DATA FIFO
FIFO
WCS AND
BUFFERS
SEQUENCERS
128-BYTE
COMMAND FIFO
DMA
CONTROL
MAILBOX
REGISTERS
CTRL/CONFIG
REGISTERS
SCSI INTERFACE
ULTRA3, LVD OR
SINGLE-ENDED
SCSI BUS
SXP
RISC
REGISTER
FILE
BOOT
CODE
MEMORY
INTERFACE
RESPONSE
QUEUE
ALU
HOST MEMORY
NVRAM
FLASH
BIOS
ADDRESS 16
DATA 16
EXTERNAL
CODE/DATA
MEMORY
Figure 1. ISP10160A Block Diagram
83116-580-00 C
ISP10160A
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