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ISL6590DR Datasheet

  • ISL6590DR

  • Digital Multi-Phase PWM Controller for Core-Voltage Regulati...

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  • INTERSIL   INTERSIL

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廬
ISL6590
Data Sheet
April 2003
FN9061
Digital Multi-Phase PWM Controller for
Core-Voltage Regulation
Processors that operate above a GHz require fast, intelligent
power systems. The Intersil ISL6590 controller offers
intelligent digital, multi-phase control that provides high
bandwidth, optimal control frequency response, noise
immunity and active transient response control algorithms.
The design is fully scalable for controlling up to six phases,
each featuring the Intersil ISL6580 intelligent power stage.
The user can configure and monitor the power system via
the Asynchronous Serial Interface (ASI). The ISL6590
controller flexibility can be extended with the addition of an
external EEPROM for updating key circuit operating
parameters in the control loop and overall system design.
The digital architecture reduces the design time for
engineers with the use of our software. The software allows
the designer the freedom to choose output stage
components and still achieve optimized system
performance.
The ISL6590 digital controller communicates with the
ISL6580 integrated power stages via 100% digital signaling.
Serial communication allows for separation of the controller
and the power stage, providing placement and layout
freedom to the power stage. The digital controller
implements phase balancing to ensure even distribution of
phase currents. The ISL6590 controller configures the
ISL6580 power stage current limit, VID reference, non-
overlap period, Active Transient Response (ATR) trigger
levels and maximum temperature limit. The digital controller
also monitors the ISL6580 power stage peak currents, over-
temperature fault, input under voltage, output over/under
voltage to ensure proper operation of the power supply.
Features
鈥?Open Architecture features software programmable
control loop compensation enabling optimal system
performance
- User accessible asynchronous serial interface
鈥?Intel VR10
- 6-bit Dynamic VID鈩?/div>
- Output voltage regulation range of 0.8375V to 1.600Vdc
鈥?250kHz to 1MHz switching frequency
鈥?100% digital control and signaling
鈥?Active Transient Response (ATR) control algorithms for
minimized voltage droop and overshoot
鈥?Controls up to six ISL6580 intelligent power stages (20A
per phase, 120A total system current)
鈥?Programmable Adaptive voltage positioning (AVP) load
line
鈥?Configurable control loop parameters (with optional
external EEPROM)
鈥?Programmable MOSFET dead time control
鈥?High speed voltage and current control loops
鈥?PWRGD and OUTEN
鈥?Serial interface to ISL6580 power stages for system
monitoring and configuration
鈥?64 Ld 9x9 QFN package
鈥?QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile.
Pinout
ISL6590 (QFN)
TOP VIEW
PLL_FILTER
PLL_ANALOG_VDD
PLL_ANALOG_VSS
PLL_DIGITAL_VDD
PLL_DIGITAL_VSS
OSC_IN
OSC_OUT
VDD_CORE
ARX
ATX
VDD_IO
SCLK
SDATA
TEST4
TEST3
ATRH
Ordering Information
PART NUMBER
ISL6590DR
TEST 2
ATRL
SOC
ERR
VDD_IO
SYS_CLK
VDD_IO
NC
NC
VDD_CORE
NC
NC
IDIG6
PWM6
NDRIVE6
TEST1
TEMP. (
o
C)
0 to 85
PACKAGE
PKG. NO.
64 Ld 9x9 QFN L64.9x9-S
OUTEN
VID [0]
VID [1]
VID [2]
VID [3]
VID [4]
VID [5]
VDD_CORE
PWRGD
VDD_IO
MCLK
MDO
MDI
MCS
NDRIVE1
PWM1
64
01
49
48
16
17
IDIG1
NDRIVE2
PWM2
IDIG2
VDD_CORE
NDRIVE3
PWM3
IDIG3
VDD_IO
NDRIVE4
PWM4
IDIG4
33
32
EXT_RESETB
NDRIVE5
PWM5
IDIG5
1
CCAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners. Dynamic VID鈩?is a trademark of Intersil Americas Inc.

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