廬
ISL6412
Data Sheet
January 2004
FN9067.0
Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit
The ISL6412 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-
clean 2.8V (LDO3). On chip logic provides sequencing
between LDO1 and LDO2 for the BBP/MAC and the I/O
supply voltage outputs. LDO3 features ultra low noise that
does not typically exceed 30碌V RMS to aid VCO stability.
High integration and the thin Quad Flat No-lead (QFN)
package makes the ISL6412 an ideal choice to power many
of today鈥檚 small form factor industry standard wireless cards
such as PCMCIA, mini-PCI and Cardbus-32.
The ISL6412 uses an internal PMOS transistor as the pass
device. The ISL6412 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET signal
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for at least 25ms after Vin has
risen above the reset threshold. FAULT1 indicates the loss
of regulation on LDO1.
Features
鈥?Small DC/DC Converter Size
- Three LDOs and Reset Circuitry in a Low-Profile
4x4mm QFN Package
鈥?High Output Current
- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
鈥?Ultra-Low Dropout Voltage
- LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA
鈥?Ultra-Low Output Voltage Noise
- <30碌V
RMS
(typ.) for LDO3 (VCO Supply)
鈥?Stable with Smaller Ceramic Output Capacitors
鈥?Extensive Protection and Monitoring Features
- Over current protection
- Short circuit protection
- Thermal shutdown
- FAULT indicator
鈥?Logic-Controlled Shutdown Pin
鈥?Integrated Microprocessor Reset Circuit
- Programmable Reset Delay
Ordering Information
PART NUMBER
ISL6412IR
ISL6412IR-TK
ISL6412IR-T5K
ISL6412IRZ
(Note)
ISL6412IRZ-TK
(Note)
TEMP. RANGE
(擄C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
PKG.
DWG. #
鈥?Proven Reference Design for a Total WLAN System
Solution
鈥?QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint Improves PCB
Efficiency and Is Thinner in Profile
鈥?Pb-Free Plus Anneal Available (RoHS Compliant)
16 Ld 4x4 QFN L16.4x4
16 Ld 4x4 QFN L16.4x4
16 Ld 4x4 QFN L16.4x4
16 Ld 4x4 QFN L16.4x4
(Pb-free)
16 Ld 4x4 QFN L16.4x4
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Applications
鈥?PRISM廬 3 Chipsets 鈥?ISL37106P
鈥?WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
鈥?Liberty Chipset
鈥?Hand-Held Instruments
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright 漏 Intersil Americas Inc. 2004. All Rights Reserved.
All Rights Reserved. PRISM廬 3 and PRISM GT鈩?are trademarks of GlobespanVirata, Inc.
All other trademarks mentioned are the property of their respective owners.
1
INTERSIL
1
2
3
4
5
6
7
8
9
10
