82C83H
March 1997
CMOS Octal Latching Inverting Bus Driver
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Features
鈥?Full 8-Bit Parallel Latching Buffer
鈥?Bipolar 8283 Compatible
鈥?Three-State Inverting Outputs
鈥?Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
鈥?Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
鈥?Single 5V Power Supply
鈥?Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
鈥?Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Ordering Information
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
SMD#
20 Pad CLCC
SMD#
20 Ld CERDIP
20 Ld PLCC
PACKAGE
20 Ld PDIP
TEMP RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
1
2
3
4
5
6
7
8
9
20 V
CC
19 DO
0
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
13 DO
6
12 DO
7
11 STB
9
OE
10
GND
11
STB
12
DO
7
13
DO
6
DI
3
DI
4
DI
5
DI
6
DI
7
4
5
6
7
8
18 DO
1
17 DO
2
16 DO
3
15 DO
4
14 DO
5
82C83H (PLCC, CLCC)
TOP VIEW
DO
0
19
V
CC
20
DI
2
DI
1
2
DI
0
1
3
GND 10
TRUTH TABLE
STB
X
H
H
鈫?/div>
H = Logic One
L = Logic Zero
X = Don鈥榯 Care
OE
H
L
L
L
DI
X
L
H
X
DO
HI-Z
H
L
鈥?/div>
PIN
DI
0
- DI
7
DO
0
- DO
7
STB
OE
PIN NAMES
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable
HI-Z = High Impedance
鈫?/div>
= Negative Transition
鈥?/div>
= Latched to Value of Last
Data
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
2971.1
4-281
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