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IS75V16F128GS32 Datasheet

  • IS75V16F128GS32

  • 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Oper...

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IS75V16F128GS32
3.0 Volt Multi-Chip Package (MCP)
鈥?128 Mbit Simultaneous Operation Flash
Memory and 32 Mbit Pseudo Static RAM
MCP FEATURES
鈥?/div>
Power supply voltage 2.7V to 3.3V
鈥?/div>
High performance:
Flash: 70ns maximum access time
PSRAM: 65ns maximum access time
ISSI
PRELIMINARY INFORMATION
MARCH 2003
廬
鈥?/div>
Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
鈥?/div>
Program Algorithms:
Automatically writes and verifies data at specified
address
鈥?/div>
Package: 107-ball BGA
鈥?/div>
Operating Temperature: -30C to +85C
鈥?/div>
Hidden ROM Region:
FLASH FEATURES
鈥?/div>
Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz:18 mA maximum
Sleep Mode: 5
碌A(chǔ)
maximum
鈥?User Configurable Banks
Flash 1 (64 Mbit)
Bank A1: 8Mbit (8KB x 8 and 64KB x 15)
Bank B1: 24Mbit (64KB x 48)
Bank C1: 24Mbit (64KB x 48)
Bank D1: 8Mbit (8KB x 8 and 64KB x 15)
Flash 2 (64 Mbit)
Bank A2: 8Mbit (8KB x 8 and 64KB x 15)
Bank B2: 24Mbit (64KB x 48)
Bank C2: 24Mbit (64KB x 48)
Bank D2: 8Mbit (8KB x 8 and 64KB x 15)
User chooses two virtual banks from a
combination of four physical banks
鈥?/div>
Simultaneous R/W Operations (dual virtual bank):
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
鈥?/div>
Data Polling and Toggle Bit:
Detects the completion of the program or erase cycle
鈥?/div>
Ready-Busy Outputs (RY/BY)
Detection of program or erase cycle completion for
each flash chip
鈥?/div>
Over 100,000 write/erase cycles
鈥?/div>
Low supply voltage (Vccf
鈮?/div>
2.5V) inhibits writes
鈥?/div>
WP/ACC
input pin:
If V
IL
, allows partial protection of boot sectors
If V
IH
, allows removal of boot sector protection
If Vacc, program time is improved
PSRAM FEATURES (32 Mb density)
鈥?/div>
Power Dissipation:
Operating: 25 mA maximum
Standby: 110 碌A(chǔ) maximum
鈥?/div>
Chip Selects:
CE1r,
CE2r
鈥?/div>
Power down feature using CE2r
Sleep Mode: 10 碌A(chǔ) maximum
Nap: 65 碌A(chǔ) maximum
8 mbit Partial: 80 碌A(chǔ) maximum
鈥?/div>
Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
鈥?/div>
Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
鈥?/div>
Data retention supply voltage: 2.1 V to 3.3V
鈥?/div>
Byte data control:
LB
(DQ0鈥揇Q7),
UB
(DQ8鈥揇Q15)
鈥?/div>
Sector Erase Architecture:
16 sectors of 4K words each and 126 sectors of 32K words
each in Word mode. Any combination of sectors, or
the entire flash can be simultaneously erased
Copyright 漏 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. 鈥?www.issi.com 鈥?/div>
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
1

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