鉂?/div>
36 mW (max.) CMOS standby
鈥?TTL compatible interface levels
鈥?Single 3.3V power supply
鈥?Fully static operation: no clock or refresh
required
鈥?Three state outputs
鈥?Available in 100-pin TQFP
鈥?Industrial temperature available
ISSI
廬
DECEMBER 2000
DESCRIPTION
The
ISSI
IS61LV6424 is a high-speed, static RAM organized
as 65,536 words by 24 bits. It is fabricated using
ISSI
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 9 ns with low power consumption.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs,
CE1,
CE2, and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory.
The IS61LV6424 is packaged in the JEDEC standard
100-pin TQFP
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
64K x 24
MEMORY ARRAY
A0-A14
ROW
DECODER
A15
X/Y
V/S
MULTIPLEX
ADDRESS
CONTROL
COLUMN
DECODER
CE1
CE2
OE
WE
CONTROL
CIRCUIT
I/O DATA
CIRCUIT
I/O0-I/O23
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
Rev. A
12/19/00
1