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IS61LPD25632T/D Datasheet

  • IS61LPD25632T/D

  • 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE...

  • 155.12KB

  • 22頁

  • ISSI   ISSI

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IS61SPD25632T/D IS61LPD25632T/D
IS61SPD25636T/D IS61LPD25636T/D
IS61SPD51218T/D IS61LPD51218T/D
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINE,
DOUBLE-CYCLE DESELECT STATIC RAM
FEATURES
鈥?Internal self-timed write cycle
鈥?Individual Byte Write Control and Global Write
鈥?Clock controlled, registered address, data and
control
鈥?Pentium鈩?or linear burst sequence control using
MODE input
鈥?Three chip enable option for simple depth expansion
and address pipelining
鈥?Common data inputs and data outputs
鈥?JEDEC 100-Pin TQFP and
119-pin PBGA package
鈥?Single +3.3V, +10%, 鈥?% power supply
鈥?Power-down snooze mode
鈥?3.3V I/O For SPD
鈥?2.5V I/O For LPD
鈥?Double cycle deselect
鈥?Snooze MODE for reduced-power standby
鈥?T version (three chip selects)
鈥?D version (two chip selects)
ISSI
廬
PRELIMINARY INFORMATION
SEPTEMBER 2000
DESCRIPTION
The
ISSI
IS61SPD25632, IS61SPD25636, S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are
high-speed, low-power synchronous static RAMs designed
to provide a burstable, high-performance, secondary cache for
the Pentium鈩? 680X0鈩? and PowerPC鈩?microprocessors.
The IS61SPD25632 and IS61LPD25632 are organized as
262,144 words by 32 bits and the IS61SPD25636 and
IS61LPD25636 are organized as 262,144 words by 36 bits.
The IS61SPD51218 and IS61LPS51218 are organized as
524,288 words by 18 bits. Fabricated with
ISSI
's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous inputs
pass through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write
enable (BWE).input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-166*
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-5
5
10
100
Units
ns
ns
MHz
*This speed available only in SPD version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. 漏 Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
PRELIMINARY INFORMATION
04/17/01
Rev. 00A
1

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