Memory. These devices offer an accelarated cycle ac-
cess called EDO Page Mode. EDO Page Mode allows
2,048 random accesses within a single row with access
cycle time as short as 20 ns per 4-bit word.
These features make the IS41C82002 and IS41LV82002
ideally suited for high-bandwidth graphics, digital signal
processing, high-performance computing systems, and
peripheral applications.
The IS41C82002 and IS41LV82002 are packaged in 28-pin
300-mil SOJ and 28-pin TSOP (Type II) with JEDEC
standard pinouts.
PRODUCT SERIES OVERVIEW
Part No.
IS41C82002
IS41LV82002
Refresh
2K
2K
Voltage
5V 鹵 10%
3.3V 鹵 10%
KEY TIMING PARAMETERS
Parameter
RAS
Access Time (t
RAC
)
CAS
Access Time (t
CAC
)
Column Address Access Time (t
AA
)
EDO Page Mode Cycle Time (t
PC
)
Read/Write Cycle Time (t
RC
)
-50
50
13
25
20
84
-60
60
15
30
25
104
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
28 Pin SOJ, TSOP (Type II)
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. 漏 Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. 鈥?1-800-379-4774
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
