鈩?/div>
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
3
2
1
DESCRIPTION
This power MOSFET is designed using the
company鈥檚 consolidated strip layout-based MESH
OVERLAY鈩?process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
s
HIGH CURRENT SWITCHING
s
UNINTERRUPTIBLE POWER SUPPLY (UPS)
s
DC/DC COVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT.
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
t ot
dv/dt(
1
)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
Gate-source Voltage
Drain Current (continuous) at T
c
= 25 C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
Total Dissipation at T
c
= 25 C
Derating F actor
Peak Diode Recovery voltage slope
Storage T emperature
Max. O perating Junction Temperature
o
o
o
Value
500
500
鹵
20
14
8.7
56
190
1.5
3.5
-65 to 150
150
(
1
) I
SD
鈮?4
A, di/dt
鈮?/div>
130 A/碌s, V
DD
鈮?/div>
V
(BR)DSS
, Tj
鈮?/div>
T
JMAX
Uni t
V
V
V
A
A
A
W
W/ C
V/ ns
o
o
o
C
C
(鈥? Pulse width limited by safe operating area
August 1998
1/8
next