鈩?/div>
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
FOR THROUGH-HOLE VERSION CONTACT
SALES OFFICE
3
1
D
2
PAK
TO-263
(Suffix 鈥漈4鈥?
DESCRIPTION
This power MOSFET is designed using the
company鈥檚 consolidated strip layout-based MESH
OVERLAY鈩?process. This technology matches
and improves the performances compared with
standard parts from various sources.
APPLICATIONS
s
HIGH CURRENT SWITCHING
s
UNINTERRUPTIBLE POWER SUPPLY (UPS)
s
DC/DC COVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT.
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
t ot
dv/dt(
1
)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
Gate-source Voltage
Drain Current (continuous) at T
c
= 25 C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
Total Dissipation at T
c
= 25 C
Derating F actor
Peak Diode Recovery voltage slope
Storage T emperature
Max. O perating Junction Temperature
o
o
o
Value
400
400
鹵
20
10
6.3
40
125
1.0
4.0
-65 to 150
150
(
1
) I
SD
鈮?0
A, di/dt
鈮?20 螒/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, Tj
鈮?/div>
T
JMAX
Uni t
V
V
V
A
A
A
W
W/ C
V/ ns
o
o
o
C
C
(鈥? Pulse width limited by safe operating area
August 1998
1/8
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