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IPU13N03LA Datasheet

  • IPU13N03LA

  • OptiMOS 2 Power-Transistor

  • 10頁

  • INFINEON   INFINEON

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IPD13N03LA
IPU13N03LA
OptiMOS
2 Power-Transistor
Features
鈥?Ideal for high-frequency dc/dc converters
鈥?Qualified according to JEDEC for target applications
鈥?N-channel
鈥?Logic level
鈥?Excellent gate charge x
R
DS(on)
product (FOM)
鈥?Very low on-resistance
R
DS(on)
鈥?Superior thermal resistance
鈥?175 擄C operating temperature
鈥?dv /dt rated
1)
廬
Product Summary
V
DS
R
DS(on),max
(SMD version)
I
D
25
13
30
V
m鈩?/div>
A
P-TO252-3-11
P-TO251-3-21
Type
IPD13N03LA
IPU13N03LA
Package
P-TO252-3-11
P-TO251-3-21
Ordering Code
Q67042-S4159
Q67042-S4160
Marking
13N03LA
13N03LA
Maximum ratings,
at
T
j
=25 擄C, unless otherwise specified
Parameter
Continuous drain current
Symbol Conditions
I
D
T
C
=25 擄C
2)
T
C
=100 擄C
Pulsed drain current
Avalanche energy, single pulse
Reverse diode dv /dt
Gate source voltage
4)
Power dissipation
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
1)
Value
30
30
210
60
6
鹵20
Unit
A
I
D,pulse
E
AS
dv /dt
V
GS
P
tot
T
j
,
T
stg
T
C
=25 擄C
3)
I
D
=24 A,
R
GS
=25
鈩?/div>
I
D
=30 A,
V
DS
=20 V,
di /dt =200 A/碌s,
T
j,max
=175 擄C
mJ
kV/碌s
V
W
擄C
T
C
=25 擄C
46
-55 ... 175
55/175/56
J-STD20 and JESD22
Rev. 1.4
page 1
2004-02-04

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