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IP100 Datasheet

  • IP100

  • PCI 10/100M Single Chip Ethernet Controller

  • 2521.34KB

  • 92頁

  • ETC

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IP100
Integrated 10/100 Ethernet MAC + PHY
1
Features
Single chip 10/100BASE, half or full duplex
Ethernet Media Access Controller
IEEE 802.3 compliant 100BASE-TX PHY
IEEE 802.3 compliant 10BASE-T PHY
IEEE 802.3 full duplex flow control
IEEE 802.3 compliant 100BASE-FX PCS
and PMA
PCI Bus master scatter/gather DMA on any
byte boundary
Full operation with PCI Clock from 12.5
MHz to 33 MHz
PCI Revision 2.2 compliant
On-chip transmit and receive FIFO buffers
On-chip LED drivers
Power management capabilities for ACPI
1.0 compliant systems
WakeOnLAN support
Management statistics gathering
IP multicast receive and filter support using
64 bit hash table
Transmit polling
Auto pad insertion for short packets
Programmable minimum Inter Packet Gap
Programmable transmit and receive FIFO
watermarks
On-chip crystal oscillator
On-chip voltage regulator
2.5/3.3V CMOS with 5V tolerant I/O
0.25碌m technology
128-pin PQFP
2
General description
The IP100 is a single-chip, full duplex, 10/100Mbps
Ethernet MAC + PHY incorporating a 32-bit PCI with
bus master support. The IP100 is designed for use in a
variety of applications including workstation NICs, PC
motherboards, and other systems utilizing a PCI bus
that require network connectivity to an Ethernet or Fast
Ethernet LAN.
The IP100 includes a PCI bus interface unit, IEEE
802.3 compliant MAC, transmit and receive FIFO
buffers, IEEE 802.3 compliant 100BASE-TX,
10BASE-T, and 100BASE-FX PHY, serial EEPROM
interface, expansion ROM interface, and LED drivers.
The IP100 implements a rich set of control and status
registers. Accessible via the PCI interface, these
registers provide a host system visibility into the
features and operating state of the IP100. Network
management statistics are also recorded, and host
access to registers of the PHY device are facilitated
through the IP100鈥檚 PCI interface.
The IP100 supports features for use in 鈥淕reen PCs鈥?or
systems where control over system power
consumption is desired. The IP100 supports several
power down states, and the ability to issue a system
鈥渨ake event鈥?via reception of unique, user defined
Ethernet frames. In addition, the IP100 can assert a
wake event in response to changes in the Ethernet link
status.
1/92
Copyright 漏 2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
IP100-DS-R03
May 27, 2003

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