AN1004
Interfacing Between LVDS and ECL /
LVECL / PECL / LVPECL
HIGH-PERFORMANCE PRODUCTS
About LVDS
As the bandwidth increases in Telecom / Datacom
and even in consumer / commercial applications ,
the high speed, low power, noise, and cost of LVDS
signal broaden the scope of its application beyond
the traditional technologies such as ECL / PECL.
LVDS (Low Voltage Differential Signaling) are differ-
ential signals with typical 350 mV swing and a DC
offset of 1.2V. When moving signals from box-to-
box or board-to-board (i.e. flat panel display). LVDS
is the right solution because it generates less noise,
consumes less power and it is very cost effective.
Figure 1 shows different voltage levels for different
types of signals.
Interfacing LVDS with PECL and LVPECL
Signal level translation between PECL / LVPECL to
LVDS can be achieved using resistor divider network;
however, when using discrete logic the signal volt-
age level would shift with respect to supply voltage
and ambient temperature fluctuation. In turn, this
will diminish the signal integrity and cause duty cycle
distortion. To avoid such problems, Semtech has
designed a fully integrated IC devices that translate
PECL / LVPECL signal into LVDS and LVDS to PECL /
LVPECL type signals. Refer to table 1 for a list of
these devices. Semtech also offers a fully integrated
receiver / driver device with true LVDS inputs and
outputs (SK1303) in an 8-lead SOIC and MSOP pack-
ages.
LVDS signals can easily be terminated with a 100
W
resistor across the differential LVDS outputs. Most
devices with LVDS I / O provide the 100W resistor
internally at its inputs to minimize component count
(i.e. SK1301). Figure 2 is an example of LVDS out-
put termination. For PECL / LVPECL output termina-
tion refer to application note AN1003.
LVDS
HSTL
PECL
LVPECL
+
0V
NC
ECL /LVECL
1
8
V
CC
-
Figure 1: Relative differences among various I/O standards
D
2
100
鈩?/div>
7
Q
LVDS
Note:
HSTL (High-Speed Transceiver Logic) signals are used in computing de-
sign applications such as memory drivers and high-speed CPU-to-Memory
D
*
3
6
Q*
RT
RT
NC
interfacing.
4
SK1301
5
V
EE
VTT
Figure 2: LVDS Termination
Revision 1/December 20, 2001
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www.semtech.com
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