TECHNICAL DATA
IN74LV164
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
The IN74LV164 is a low-voltage Si-gate CMOS device and is pin
and function compatible with the IN74HC/HCT164.
The IN74LV164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (DSA or DSB); either input can be
used as an active HIGH enable for data entry through the other input.
Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition
of the clock (CP) input and enters into Q
0
, which is the logical AND of
the two data inputs (DSA, DSB ) that existed one set-up time prior to the
rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs
and clears the register asynchronously, forcing all outputs LOW.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 5.5 V
Low Input Current: 1.0
碌A(chǔ),
0.1
碌脌
at 脪 = 25
擄脩
Output Current: 6 mA at V
CC
= 3.0 V; 12 mA at V
CC
= 4.5 V
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
14
1
14
1
ORDERING INFORMATION
D SUFFIX
SO
IN74LV164N
IN74LV164D
IZ74LV164
Plastic DIP
SOIC
chip
T
A
= -40擄 to 125擄 C for all packages
PIN ASSIGNMENT
DSA 1
DSB
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q7
Q6
Q5
Q4
MR
CP
LOGIC DIAGRAM
Q0
Q1
1
SERIAL DSA
DATA
2
INPUTS DSB
Q2
2 Q0
DATA
4
Q1
Q3
GND
PARALLEL
DATA
OUTPUTS
5 Q2
6 Q3
10 Q 4
11 Q 5
12 Q 6
CP
8
13 Q 7
FUNCTION TABLE
Inputs
Outputs
DSB
X
L
H
L
H
Q0
L
L
L
L
H
Q1 ... Q7
L 鈥?L
Q0 ... Q6
Q0 ... Q6
Q0 ... Q6
Q0 ... Q6
MR
L
H
CP
X
DSA
X
L
L
H
H
MR
9
PIN 14=V
CC
PIN 7 = GND
H
H
H
H = high voltage level
L = low voltage level
X = don鈥檛 care
INTEGRAL
1
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