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IN74HCT109 Datasheet

  • IN74HCT109

  • DUAL J-K FLIP-FLOP WITH SET AND RESET

  • 5頁(yè)

  • INTEGRAL

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IN74HCT109
D
UAL
J-K F
LIP
-F
LOP
WITH SET AND
R
ESET
High-Performance Silicon-Gate CMOS
The IN74HCT109 is identical in pinout to the LS/ALS109. The
IN74HCT109 may be used as a level converter for interfacing
TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-
K
flip-flops with individual set,
reset, and clock inputs. Changes at the inputs are reflected at the
outputs with the next low-to-high transition of the clock. Both Q to
Q
outputs are available from each flip-flop.
鈥?/div>
TTL/NMOS Compatible Input Levels
鈥?/div>
Outputs Directly Interface to CMOS, NMOS, and TTL
鈥?/div>
Operating Voltage Range: 4.5 to 5.5 V
鈥?/div>
Low Input Current: 1.0
碌A(chǔ)
ORDERING INFORMATION
IN74HCT109N Plastic
IN74HCT109D SOIC
T
A
= -55擄 to 125擄 C for all
packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Set
L
H
L
H
H
H
H
H
Inputs
Reset Clock
H
L
L
H
H
H
H
H
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Output
Q
Q
H
L
L
H
*
H
H
*
L
H
Toggle
No
Change
H
L
No
Change
PIN 16=V
CC
PIN 8 = GND
L
X = Don鈥檛 care
*
Both outputs will remain high as long as
Set and Reset are low., but the output
states are unpredictable if Set and Reset
go high simultaneously.
1

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