IN74ACT192
P
RESETTABLE
BCD/D
ECADE
UP/DOWN C
OUNTER
High-Speed Silicon-Gate CMOS
The IN74ACT192 is identical in pinout to the LS/ALS192,
HC/HCT192. The IN74ACT192 may be used as a level converter
for interfacing TTL or NMOS outputs to High Speed CMOS
inputs.
The counter has two separate clock inputs, a Count Up Clock
and Count Down Clock inputs. The direction of counting is
determined by which input is clocked. The outputs change state
synchronous with the LOW-to-HIGH transitions on the clock
inputs. This counter may be preset by entering the desired data
on the P0, P1, P2, P3 input. When the Parallel Load input is
taken low the data is loaded independently of either clock input.
This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the
counter can also be cleared. This is accomplished by inputting a
high on the Master Reset input. All 4 internal stages are set to
low independently of either clock input.Both a Terminal Count
Down (TC
D
) and Terminal Count Up (TC
U
) Outputs are provided
to enable cascading of both up and down counting functions.
The TC
D
output produces a negative going pulse when the
counter underflows and TC
U
outputs a pulse when the
counter overflows. The counter can be cascaded by
connecting the TC
U
and TC
D
outputs of one device to the
Count Up Clock and Count Down Clock inputs, respectively,
of the next device.
鈥?/div>
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
碌A(chǔ);
0.1
碌A(chǔ)
@ 25擄C
Outputs Source/Sink 24 mA
LOGIC DIAGRAM
ORDERING INFORMATION
IN74ACT192N Plastic
IN74ACT192D SOIC
T
A
= -40擄 to 85擄 C for all
packages
PIN ASSIGNMENT
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
PIN 16 =V
CC
PIN 8 = GND
1
IN74ACT192N相關(guān)型號(hào)PDF文件下載
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