IMSA110
IMAGE AND SIGNAL PROCESSING SUB鈥揝YSTEM
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1-D/2-D SOFTWARE CONFIGURABLE CON-
VOLVER/FILTER
ON-CHIP PROGRAMMABLE LINE DELAYS (0
鈥?1120 STAGES)
8-BIT DATA AND 8.5-BIT COEFFICIENT
SLICE
21 MULTIPLY-AND-ACCUMULATE STAGES
1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN-
DOW
ON-CHIP POST PROCESSOR FOR DATA
TRANSFORMATION
FULLY CASCADABLE IN WINDOW SIZE AND
ACCURACY
20 MHZ DATA THROUGHPUT (420 MOPS)
SIGNED/UNSIGNED DATA AND COEFFI-
CIENTS
MICROPROCESSOR INTERFACE
HIGH SPEED CMOS IMPLEMENTATION
TTL COMPATIBLE
SINGLE +5V
鹵
10% SUPPLY
POWER DISSIPATION < 2.0 WATTS
100 PIN CERAMIC PGA
PGA100
(Ceramic Grid Array Package)
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APPLICATIONS
1-D and 2-D digital convolution and correlation
Real time image processing and enhancement
Edge and feature detection
Data transformation and histogram equalisa-
tion
Computer vision and robotics
Template matching
Pulse compression
1-D or 2-D interpolation
July 1992
ORDERING INFORMATION
Part Number
IMSA110-G20S
Package
PGA100
A110-01.TBL
Clock
Speed
20MHz
Military/
commercial
commercial
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