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IMP16C554-LJ68 Datasheet

  • IMP16C554-LJ68

  • Quad Universal Asynchronous Receiver/Transmitter (UART) with...

  • 493.35KB

  • 20頁

  • IMP

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IMP16C554
Data Communications
Quad Universal Asynchronous
Receiver/Transmitter (UART)
with FIFO's
Description
The IMP16C554 is a universal asynchronous receiver and
transmitter with 16 byte transmit and receive FIFO. A
programmable baud rate generator is provided to select
transmit and receive clock rates from 50Hz to 1.5MHz.
The IMP16C554 is an improved version of the IMP16C550
UART with higher operating speed and lower access time.
The IMP16C554 on board status registers provides the
error conditions, type and status of the transfer operation
being performed. Included is complete MODEM control
capability, and a processor interrupt system that may be
software tailored to the user鈥檚 requirements. The
IMP16C554 provides internal loop-back capability for on
board diagnostic testing.
The IMP16C554 is fabricated in an advanced 1.2u CMOS
process to achieve low drain power and high speed
requirements.
Key Features
16 byte receive FIFO with error flags
Modem control signal (CTS*, RTS*, DSR*, DTR*,
RI* ,CD*)
Programmable character lengths(5,6,7,8)
Even, odd, or no parity bit generation and detection
Status report register
Independent transmit and receive control
TLL compatible inputs. outputs
Software compatible with Ei8250, 1Ei16C550
460.8kHz transmit/receive operation with 7.372
MHz crystal or external clock source
Pin Configuration
CDA鈥?/div>
RIA鈥?/div>
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID鈥?/div>
CDO鈥?/div>
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CDA鈥?/div>
RIA鈥?/div>
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
RXD
RID鈥?/div>
COD鈥?/div>
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
CDB鈥?/div>
RIB鈥?/div>
RXB鈥?/div>
VCC
NC
A2
A1
A0
XTAL1
XTAL2
ERSET
RXRDY鈥?/div>
TXRD鈥?/div>
GND
RXC
RIC鈥?/div>
CDC鈥?/div>
68-PIN PLCC
1
408-432-9100/www.impweb.com
DSBS鈥?/div>
CDS鈥?/div>
RIB鈥?/div>
RXB鈥?/div>
VCC
A2
A1
A0
XTAL1
XTAL2
RESET
GND
RXC
RIC鈥?/div>
CDC鈥?/div>
DSRC鈥?/div>
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DSRA鈥?/div>
CTSA鈥?/div>
DTRA鈥?/div>
VCC
RTSA鈥?/div>
INTA
CSA鈥?/div>
TXA
IOW鈥?/div>
TXB
CSB鈥?/div>
INTB
RTSB鈥?/div>
GND
DTRB
CTSD鈥?/div>
DSRB鈥?/div>
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
IMP
16C554
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DSRD鈥?/div>
CTSD鈥?/div>
DTRD鈥?/div>
GND
RTSD鈥?/div>
INTD
CSD鈥?/div>
TXD
IOR鈥?/div>
TXC
CSC鈥?/div>
INTC
RTSC鈥?/div>
VCC
DTRC鈥?/div>
CTSC鈥?/div>
DSRC鈥?/div>
DSRA鈥?/div>
CTSA鈥?/div>
DTRA鈥?/div>
VCC
RTSA鈥?/div>
INTA
CSA鈥?/div>
TXA
IOW鈥?/div>
TXB
CSB鈥?/div>
INTB
RTSB鈥?/div>
GND
DTRB
CTSD鈥?/div>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IMP
16C554
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DSRD鈥?/div>
CTSD鈥?/div>
DTRD鈥?/div>
GND
RTSD鈥?/div>
INTD
CSD鈥?/div>
TXD
IOR鈥?/div>
TXC
CSC鈥?/div>
INTC
RTSC鈥?/div>
VCC
DTRC鈥?/div>
CTSC鈥?/div>
64-PIN QFP
漏 2002 IMP, Inc.

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