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IMISG750CYB Datasheet

  • IMISG750CYB

  • CPU System Clock Generator

  • 15頁(yè)

  • ETC

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SG750
Low EMI Clock Generator for ALI-M1541 for Socket 7 with AGP Boards and Mobile
Pentium
廬
II Designs.
Approved Product
FREQUENCY TABLE (MHz)
PRODUCT FEATURES
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
CPU
60
66.8
50
75
75
83.3
90.0
100
AGP
60
66.8
50
75
50
55.53
60.0
66.6
PCI
30
33.4
25
37.5
25
27.77
30.0
33.3
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Supports Pentium ,Pentium II, M2 & K6 CPUs.
廬
Supports Mobile Pentium II
Supports Synchronous and Asynchronous PCI.
3 CPU clocks
3 AGP clocks
Up to 12 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
Optional common or mixed supply mode:
(VDD = VDDP = VDDC = 3.3V) or
(VDD = VDDP = 3.3V, VDDC = 2.5V)
< 250ps skew among CPU or SDRAM clocks
< 250ps skew among PCI clocks
2
I C 2-Wire serial interface
Programmable registers featuring:
- Jumperless frequency selection
- enable/disable each output pin
- mode as tri-state, test, or normal
Power Management Capability
48 MHz for USB support
Internal Crystal Load Capacitors
48-pin SSOP package
Spread Spectrum Technology for EMI reduction
廬
廬
CONNECTION DIAGRAM
IMISG750
VDD
REF/SW15
VSS
XIN
XOUT
VDDP
PCI_F/S1
PCI0/S2
VSS
PCI1
PCI2
PCI3
PCI4
VDDP
PCI5/SDIN
VSS
CPU_STP#/SDRAM11
PCI_STP#/SDRAM10
VDDS
AGP_STP#/SDRAM9
PWR_DWN#/SDRAM8
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BLOCK DIAGRAM
XIN
REF
XOUT
REF
VDDC
SW15
PCI_STP#
CPU_STP#
3
VDDP
4
CPU (0:2)
PCI (1:4)
AGP_STP#
PWR_DWN#
S2
S1
SDIN
S0
MODE
2
PCI (0_F)
PCI5
VDDP
9
VDDS
2
SDRAM (0:7)
SDRAM_FB
AGP (1:2)
AGP0
SDRAM (8:11)
SDATA
SCLK
CONTROL
LOGIC
4
VDDA
VDDA
AGP1
AGP2
VSS
CPU0
CPU1
VDDC
CPU2
SDRAM_FB
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VSS
48MHZ / S0
AGP0 / MODE
PLL2
48 MHz
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.8
8/10/98
Page 1 of 15

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