SG745
I
2
C Clock Generator for SiS5591/2, or VIA MVP3, 3 DIMM, Socket 7 Designs with AGP Support.
Approved Product
PRODUCT FEATURES
FREQUENCY TABLE (MHz)
SD
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
60
66.8
50
75
75
83.3
90
100
60
66.8
50
75
75
83.3
90
100
PCI
30
33.4
25
37.5
32
32
30
33.3
30
33.4
25
37.5
32
32
30
33.3
AGP
60
66.8
50
64
64
64
60
66.6
60
66.8
50
64
64
64
60
66.6
SDRAM
60
66.8
50
64
64
64
60
66.6
60
66.8
50
75
75
83.3
90
100
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Supports Pentium , Pentium II, M2,& K6 CPUs.
Designed to support SiS5591/2 and MVP3 logic.
4 CPU & 2 (Sync./ Async.) AGP clocks
Up to 12 SDRAM clocks for 3 DIMMs.
6 (Sync./ Async.) PCI clocks.
Optional common or mixed supply mode:
(VDD = VDDPCI = VDDCPU = 3.3V) or
(VDD = VDDPCI = 3.3V, VDDCPU = 2.5V)
< 250ps skew among CPU or SDRAM clocks.
< 250ps skew among PCI clocks.
2
I C 2-Wire serial interface
Programmable registers featuring:
- Jumperless frequency selection
- enable/disable each output pin
- mode as tri-state, test, or normal
Power Management Capability.
48 MHz for USB support
Internal Crystal Load Capacitors.
48-pin SSOP package
Spread Spectrum Technology for EMI reduction
廬
廬
CONNECTION DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
AGP2
REF1/SD_SEL#
VSS
CPU0
CPU1
VDDCPU
CPU2
CPU3
VSS
SDRAM0
SDRAM1
VDDSD0
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDSD1
SDRAM6
SDRAM7
VSS
48MHZ/S0
24 MHZ/MODE
BLOCK DIAGRAM
REF
XIN
XOUT
REF0
REF1
SD_Sel# CS#
VDDCPU
B
S2
S1
S0
MODE
dly
4
6
2
CPU (0:3)
PCI (F, 0:4)
AGP (1:2)
B
B
B
PLL1
12
SDRAM(0:11)
SDATA
SCLK
48 MHz
PLL2
VDD
REF0/CS#
VSS
XIN
XOUT
VDDPCI
PCI_F/S1
FCI0/S2
VSS
PCI1
PCI2
PCI3
PCI4
VDDPCI
AGP1
VSS
SDRAM11
SDRAM10
VDDSD2
SDRAM9
SDRAM8
VSS
SDATA
SCLK
24 MHz
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.7
8/14/98
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