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IMISC674BYB Datasheet

  • IMISC674BYB

  • CPU System Clock Generator

  • 11頁

  • ETC

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SC674
I
2
C Clock Generator for Pentium
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and Pentium
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II with 440LX
Chipset and 4 DIMMs
Approved Product
PRODUCT FEATURES
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Supports
Pentium & Pentium II using the
440LX chipset.
.
5 CPU / AGP clocks
Up to 16 SDRAM clocks for 4 DIMMs.
7 PCI synchronous clocks.
Optional common or mixed supply mode:
(VDD = VDDP = VDDC = 3.3V) or
(VDD = VDDP = 3.3V, VDDC = 2.5V)
Supports Power Management
< 250ps skew CPU and SDRAM clocks.
< 250ps skew among PCI clocks.
I
2
C 2-Wire serial interface
Programmable registers featuring:
- enable/disable each output pin
- mode as tri-state, test, or normal
3 IOAPIC clocks for multiprocessor support.
56-pin SSOP package
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FREQUENCY TABLE
SEL
0
1
CPU
60.0
66.6
PCI
30.0
33.3
CONNECTION DIAGRAM
VDD
IOAPIC3
REF
VSS
XIN
XOUT
VDDP
PCICLK_F
PCICLK1
VSS
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDP
PCICLK6
VSS
SDRAM12
SDRAM11
VDDP
SDRAM10
SDRAM9
VSS
SDRAM16
SDRAM15
VDDP
SDATA
SDCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDC
IOAPIC1
IOAPIC2
VSS
CPUCLK1
CPUCLK2
VDDC
CPUCLK3
CPUCLK4
VSS
CPUCLK5
SDRAM1
SDRAM2
VDDP
SDRAM3
SDRAM4
VSS
SDRAM5
SDRAM6/ PD#
VDDP
SDRAM7 / CS#
SDRAM8 / PS#
VSS
SDRAM13
SDRAM14
VSS
Sel
Mode
BLOCK DIAGRAM
XIN
REF
REF
XOUT
IOAPIC(1:3)
VDDC
VDDC
Sel
Sdata
Sclock
PS#
CS#
PD#
PLL
Clock
Gen.
B
5
dly
CPUCLK(1:5)
B
6
PCICLK(1:6)
PCICLK_F
B
B
16
SDRAM(1:5, 9:16)
SDRAM(1:16)
Mode
PS# : PCI_STOP#
CS# : CPU_STOP#
PD# : PWR_DWN#
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev. 1.7
4/23/97
Page 1 of 11

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