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IMIC9850A Datasheet

  • IMIC9850A

  • Clocks and Buffers

  • 19頁(yè)

  • ETC

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ADVANCED INFORMATION
C9850
High Performance Pentium
餂?/div>
III Clock Generator
Product Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Four differential host clocks
Two 3V Mref single ended for DRCG
Four 3V, 66 MHz clocks
Ten 3V, 33 MHz PCI clocks
Two 48 MHz clocks
Two 14.318 MHz reference clocks
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
frequency selection
External resistor for CPU current reference
56 Pin SSOP and TSSOP Package
Product Description
This device is an advanced performance single
package clock solution for high end Pentium III designs
using Rambus memory system architectures. It
provides all of the system motherboard鈥檚 clocks
needed to support the CPU, memory and peripheral
devices. Included in the frequency table are specific
+5% margin test frequencies to assist designers in
verification of adequate timing margins in designs. All
CPU (Host) clocks are deferential and comply with Intel
specified timing requirements.
Frequency Selection Table
SEL 100/133
0
0
0
0
1
1
1
1
SELA
0
0
1
1
0
0
1
1
SELB
0
1
0
1
0
1
0
1
CPU(1:4),
CPU# (1:4)
100 MHz
105 MHz
200 MHz
High Z
133.3 MHz
126.7 MHz
200 MHz
XIN/2
3VMRef/
3VMRef_b
50 MHz
52.5 MHz
50 MHz
High Z
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
3V66
(0:3)
66.7 MHz
70.0 MHz
66.7 MHz
High Z
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
PCI (0:9)
33.3 MHz
35.0 MHz
33.3 MHz
High Z
33.3 MHz
31.7 MHz
33.3 MHz
XIN/8
48 M (0:1)
48 MHz
48 MHz
48 MHz
High Z
48 MHz
48 MHz
48 MHz
XIN/2
REF (1:2)
14.318 MHz
14.318 MHz
14.318 MHz
High Z
14.318 MHz
14.318 MHz
14.318 MHz
XIN
Block Diagram
Sel1
XIN
XOUT
VDDR
Ref1/MultSel0
Ref2/MultSel1
Sel2
VSSR
3VMRef
3VMRef_b
Spread#
SEL100/133
PwrDwn#
Pin Configuration
VSSR
Ref1/MultSel0
Ref2/MultSel1
VDDR
XIN
XOUT
VSSP
PCI0
PCI1
VDDP
PCI2
PCI3
VSSP
PCI4
PCI5
VDDP
PCI6
PCI7
VSSP
PCI8
PCI9
VDDP
SEL100/133
VSSU
48M0/SelA
48M1/SelB
VDDU
PwrDwn#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDM
3VMRef
3VMRef_b
VSSM
Spread#
CPU1
CPU1#
VDDC
CPU2
CPU2#
VSSC
CPU3
CPU3#
VDDC
CPU4
CPU4#
VSSC
I_Ref
VDD
VSS
VDD
3V66_0
3V66_1
VSS
VSSL
3V66_2
3V66_3
VDDL
OSC
VCO1
I_REF
VDDC
CPU(1:4)
CPU#(1:4)
VSSC
VDDL
3V66(0:3)
VSSL
VDDP
PCI (0:9)
VSSP
VCO2
SELA/B
2
VDDU
48M(0:1)/Sel(A:B)
VSSU
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 1 of 19

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