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IMIC9630 Datasheet

  • IMIC9630

  • Clocks and Buffers

  • 18頁(yè)

  • ETC

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APPROVED PRODUCT
C9630
PC133 Clock Generator for SiS630/Pentium
廬
III & SiS540/Socket7 Applications
Product Features
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Supports Pentium芒III, K6, and Socket 7 CPU鈥檚
Designed to SiS630 & SiS540 Chipset requirements
3 copies of CPU Clock (CPU[0:2] )
14 copies of SDRAM Clock (SDRAM[0:13]
7 copies of PCI Clock
2 REF(0:1) Clock outputs
1 USB Clock (Non SSC), 48MHz
1 programmable SIO (Non SSC), 24/48MHz
133 MHz SDRAM support
Cypress Spread Spectrum for best EMI reduction
SMBus Support with read back capabilities.
Dial-a-Frequency鈩?Feature
48 Pin SSOP package.
Frequency Table (MHz)
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.9
97.2
70.0
95.0
95.0
112.0
97.0
96.0
SDRAM
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.9
97.2
105.0
95.0
126.7
112.0
129.3
96.0
PCICLK
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.4
35.0
31.6
31.6
37.3
32.4
32.0
Block Diagram
30pF
Xin
300K
1
30pF
VDD
Xout
1
REF0/S3
VDD
REF1
Table 1
Note: *Programmable to 48 MHz via SMBus
Pin Configuration
VDD
S3 / REF0
VSS
XIN
XOUT
VDD
S1/ PCI0
S2 / PCI1
PCI2
VSS
PCI3
PCI4
PCI5
PCI6
VDD
VSS
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
VSS
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDC
CPU0
CPU1
VSS
CPU2
VDD
SDRAM13
SDRAM12
VSS
SDRAM11
SDRAM10
VDD
SDRAM9
SDRAM8
VSS
SDRAM7
SDRAM6
VDD
SDRAM5
SDRAM4
VDD
S0 / 48MHz
24_48MHz
VDDcpu
Rin
cpu
3
CPU(0:2)
VDD
s3
s2
s1
s0
SDATA
SCLK
sdata
sclk
PLL1
sdram
14
VDD
5
pci
1
VDD
PCI0/S1
PCI(2:6)
SDRAM(0:13)
VDD
1
PCI1/S2
Rin
i2c-clk
i2c-data
48
1
VDD
VDD
1
48MHz/S0
24 or 48
PLL2
24_48MHz
Fig.1
Fig.2
Cypress Semiconductor Corporation
3901 North First St.
San Jose, CA 95134. Tel: 408-943-2600
http://www.cypress.com
Document #: 38-07035 Rev. *A
12/18/2002
Page 1 of 18

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