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IMIB9948 Datasheet

  • IMIB9948

  • Clocks and Buffers

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B9948
3.3V, 160MHz, 1:12 Clock Distribution Buffer
Product Features
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160MHz Clock Support
LVPECL or LVCMOS/LVTTL Clock Input
LVCMOS/LVTTL Compatible Inputs
12 Clock Outputs: Drive up to 24 Clock Lines
Synchronous Output Enable
Output Tri-state Control
350ps Maximum Output-to-Output Skew
Pin Compatible with MPC948
Industrial Temp. Range: -40擄C to +85擄C
32-Pin TQFP Package
Description
The B9948 is a low voltage clock distribution buffer with
the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well
as the primary system clock. All other control inputs are
LVCMOS/LVTTL compatible. The twelve outputs are
3.3V LVCMOS or LVTTL compatible and can drive two
series terminated 50鈩?transmission lines. With this
capability the B9948 has an effective fan-out of 1:24.
The outputs can also be tri-stated via the tri-state input
TS#. Low output-to-output skews make the B9948 an
ideal clock distribution buffer for nested clock trees in
the most demanding of synchronous systems.
The B9948 also provides a synchronous output enable
input for enabling or disabling the output clocks. Since
this input is internally synchronized to the input clock,
potential output glitching or runt pulse generation is
eliminated.
Block Diagram
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
0
1
VDDC
Pin Configuration
VDDC
VDDC
26
VSS
VSS
Q0
Q1
Q2
27
12
Q0-Q11
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
32
31
30
29
28
25
24
23
22
21
20
19
18
17
16
Q3
B9948
9
10
11
12
13
14
15
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Figure 1
Q11
Q10
VSS
VDDC
VDDC
VSS
Q9
Q8
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07079 Rev. *A
06/18/2001
Page 1 of 7

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