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160MHz Clock Support
LVCMOS/LVTTL Compatible Inputs
10 Clock Outputs: Drive up to 20 Clock Lines
1X or 1/2X Configurable Outputs
Output Tri-state Control
250ps Maximum Output-to-Output Skew
Pin Compatible with MPC946
Industrial Temp. Range: -40擄C to +85擄C
32-Pin TQFP Package
Description
The B9946 is a low voltage clock distribution buffer with
the capability to select one of two LVCMOS/LVTTL
compatible input clocks. These clock sources can be
used to provide for test clocks as well as the primary
system clocks. All other control inputs are
LVCMOS/LVTTL compatible. The 10 outputs are 3.3V
LVCMOS or LVTTL compatible and can drive two
series terminated 50鈩?transmission lines. With this
capability the B9946 has an effective fan-out of 1:20.
The B9946 is capable of generating 1X and 1/2X
signals from a 1X source. These signals are generated
and retimed internally to ensure minimal skew between
the 1X and 1/2X signals. SEL(A:C) inputs allow flexibility
in selecting the ratio of 1X to1/2X outputs.
The B9946 outputs can also be tri-stated via MR/OE#
input. When MR/OE# is set high, it resets the internal
flip-flops and tri-states the outputs.
Block Diagram
Pin Configuration
MR/OE#
TCLK_SEL
TCLK0
TCLK1
0
1
R
0
1
/1
/2
VDDC
32
31
30
29
28
27
26
3
QA0:2
DSELA
0
1
3
QB0:2
TCLK_SEL
VDD
TCLK0
TCLK1
DSELA
DSELB
DSELC
VSS
1
2
3
4
5
6
7
8
9
25
24
23
22
21
20
19
18
17
16
VDDC
QA0
QA1
QA2
VSS
VSS
B9946
10
11
12
13
14
15
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
VDDC
DSELB
0
1
VSS
QC0
QC1
QC2
VSS
VDDC
4
QC0:3
DSELC
MR/OE#
Figure 1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07077 Rev. *A
VDDC
QC3
06/18/2001
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