ILD615
QUAD CHANNEL
ILQ615
DUAL CHANNEL
FEATURES
鈥?Identical Channel to Channel Footprint
鈥?Current Transfer Ratio (CTR) Range at
I
F
=10 mA
ILD/Q615-1: 40 鈥?80% Min.
ILD/Q615-2: 63 鈥?125% Min.
ILD/Q615-3: 100 鈥?200% Min.
ILD/Q615-4: 160 鈥?320% Min.
鈥?Guaranteed CTR at I
F
=1 mA
ILD/Q615-1: 13% Min.
ILD/Q615-2: 22% Min.
ILD/Q615-3: 34% Min.
ILD/Q615-4: 56% Min.
鈥?High Collector-Emitter Voltage BV
CEO
=70 V
鈥?Dual and Quad Packages Feature:
- Reduced Board Space
- Lower Pin and Parts Count
- Better Channel to Channel CTR Match
- Improved Common Mode Rejection
鈥?Field-Effect Stable by TRIOS (TR
ansparent
IO
n
S
hield
)
鈥?Isolation Test Voltage from Double Molded
Package, 5300 VAC
RMS
鈥?UL Approval #E52744
鈥?VDE #0884 Available with Option 1
Maximum Ratings
(Each Channel)
Emitter
Reverse Voltage ................................................ 6 V
Forward Current ........................................... 60 mA
Surge Current .................................................1.5 A
Power Dissipation ...................................... 100 mW
Derate Linearly from 25
擄
C ................... 1.33 mW/
擄
C
Detector
Collector-Emitter Reverse Voltage .................. 70 V
Emitter-Collector Reverse Voltage .................... 7 V
Collector Current .......................................... 50 mA
Collector Current (t <1 ms) .........................100 mA
Power Dissipation ...................................... 150 mW
Derate Linearly from 25
擄
C........................ 2 mW/
擄
C
Package
Storage Temperature................... 鈥?5
擄
C to +150
擄
C
Operating Temperature ............... 鈥?5
擄
C to +100
擄
C
Junction Temperature.................................... 100
擄
C
Soldering Temperature
(2 mm distance from case bottom) ........... 260
擄
C
Package Power Dissipation, ILD615.......... 400 mW
Derate Linearly from 25
擄
C.................. 5.33 mW/
擄
C
Package Power Dissipation, ILQ615 ......... 500 mW
Derate Linearly from 25
擄
C................. 6.67 mW/
擄
C
Isolation Test Voltage (t=1 sec.)........ 5300 VAC
RMS
Creepage ............................................... 7 mm min.
Clearance............................................... 7 mm min.
Isolation Resistance
V
IO
=500 V, T
A
=25
擄
C ...............................
鈮?/div>
10
12
鈩?/div>
V
IO
=500 V, T
A
=100
擄
C .............................
鈮?/div>
10
11
鈩?/div>
.790 (20.07)
.779 (19.77 )
.045 (1.14)
.030 (.76)
PHOTOTRANSISTOR OPTOCOUPLER
Dimensions in inches (mm)
4
3
2
1
Pin One I.D.
Anode 1
8
7
6
5
Collector
Emitter
Collector
Emitter
.268 (6.81)
.255 (6.48)
5
6
7
8
Cathode 2
Anode 3
.390 (9.91)
.379 (9.63)
.045 (1.14)
.030 (.76)
Cathode 4
.150 (3.81)
.130 (3.30)
.305 Typ.
(7.75) Typ.
.135 (3.43)
.115 (2.92)
4擄
Typ.
.022 (.56)
.018 (.46)
.040 (1.02)
.030 (.76 )
.100 (2.54) Typ.
10
擄
Typ.
3擄鈥?擄
.012 (.30)
.008 (.20)
Pin
One
I.D.
Anode 1
Cathode 2
Anode 3
16 Collector
15 Emitter
14 Collector
13 Emitter
12 Collector
11 Emitter
10 Collector
9 Emitter
.268 (6.81)
.255 (6.48)
Cathode 4
Anode 5
Cathode 6
Anode 7
Cathode 8
.150 (3.81)
.130 (3.30)
.305 Typ.
(7.75) Typ.
4擄
Typ.
.022 (.56)
.018 (.46)
.040 (1.02)
.030 (.76 )
.100 (2.54) Typ.
10
擄
Typ.
3擄鈥?擄
.012 (.30)
.008 (.20)
.135 (3.43)
.115 (2.92)
DESCRIPTION
The ILD/Q615 are multi-channel phototransistor optocouplers that use GaAs
IRLED emitters and high gain NPN phototransistors. These devices are con-
structed using over/under leadframe optical coupling and double molded
insulation technology resulting a Withstand Test Voltage of 7500 VAC
PEAK
and a Working Voltage of 1700 VAC
RMS
.
The binned min./max. and linear CTR characteristics combined with the
TRIOS (TRansparent IOn Shield) 鏗乪ld-effect process make these devices
well suited for DC or AC voltage detection. Eliminating the phototransistor
base connection provides added electrical noise immunity from the tran-
sients found in many industrial control environments.
Because of guaranteed maximum non-saturated and saturated switching
characteristics, the ILD/Q615 can be used in medium speed data I/O and
control systems. The binned min./max. CTR speci鏗乧ation allow easy worst
case interface calculations for both level detection and switching applica-
tions. Interfacing with a CMOS logic is enhanced by the guaranteed CTR at
an I
F
=1 mA.
See Appnote 45, 鈥淗ow to Use Optocoupler Normalized Curves.鈥?/div>
5鈥?
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英文版
PHOTODARLINGTON OPTOCOUPLER
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英文版
PHOTODARLINGTON OPTOCOUPLER
SIEMENS [S...
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英文版
Optocoupler, Phototransistor Output, Dual Channel
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英文版
DUAL PHOTOTRANSISTOR OPTOCOUPLER
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英文版
Optocoupler, Phototransistor Output, Dual Channel
VISAY [Vis...
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英文版
DUAL PHOTOTRANSISTOR OPTOCOUPLER
SIEMENS [S...
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英文版
Optocoupler, Phototransistor Output (Dual, Quad Channel)
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英文版
PHOTOTRANSISTOR OPTOCOUPLER
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英文版
PHOTOTRANSISTOR OPTOCOUPLER
SIEMENS [S...
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Optocoupler, Phototransistor Output (Dual, Quad Channel)
VISAY [Vis...
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AC INPUT PHOTOTRANSISTOR OPTOCOUPLER
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Optocoupler, Phototransistor Output, AC Input (Dual, Quad Ch...
VISAY [Vis...
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英文版
AC INPUT PHOTOTRANSISTOR OPTOCOUPLER
SIEMENS [S...
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英文版
Optocoupler, Phototransistor Output (Dual, Quad Channel)
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MULTI-CHANNEL PHOTOTRANSISTOR OPTOCOUPLER
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英文版
MULTI-CHANNEL PHOTOTRANSISTOR OPTOCOUPLER
SIEMENS [S...
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英文版
Optocoupler, Phototransistor Output (Dual, Quad Channel)
VISAY [Vis...
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英文版
AC INPUT PHOTOTRANSISTOR OPTOCOUPLER
1
2
3
4
5
