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01/99
IFPA300, IFPA301
Monolithic JFET Preamplifier
Description & Features
The IFPA300 series is an inverting transimpedance
amplifier featuring extremely low noise and a wide
gain-bandwidth suitable as a charge-sensitive pre-
amplifier for a broad range of applications.
The monolithic IFPA300 series contain 8 n-channel
epitaxial-channel diffused-gate JFETs to achieve
optimally low 1/f noise performance over a wide
temperature range (120K-300K).
DC open loop gain
GBW
e
N
@ 10 Hz
爐
85 dB
200 MHz
3.0 nV/鈭欻z
Absolute maximum ratings at TA = 25擄C
All pins (except Input) referenced to Bias 3
Input to Bias 3
Power Dissipation
Derating Factor
Operating Temperature
85 dB
脴V
225 mW
1.8 mW/擄C
150擄C
At this time, there are two units in this family.
The 300/301 Series gives more flexibility with respect
to output transistor drain.
The 310/311 Series ties the output transistor drain to
the V
DD
line.
Simplified Schematic Circuit
General Specifications
Power Dissipation at VDD = 12 V
Input Leakage Current (T = 300 K)
Input-Referred Noise Voltage (f = 10 kHz)
Input-Referred Noise Voltage (f = 10 Hz)
Output Range at VDD = 12 V
Designed to drive 50鈩?load.
<100 mW
10 pA
0.6 nV/鈭欻z
3.0 nV/鈭欻z
4.0 V (5.0 V Max)
J
4
J
7
J
3
V
DD
Substrate
Charge Sensitive
Preamplifier Specifications
The IFPA300 Series is actually tailored to detector
capacitance in the 100 脨 1000 pF range.
Input Open-Loop Capacitance
Rise Time (CD = 500 pF, Cf = 33 pF)
60 pF
20 ns
Bias 1
J
2
J
6
J
8
Open
Drain
Output
Open
Source
Output
Bias 2
Input
J
1
J
5
V
SS
Equivalent Noise Charge
(Measured with semigaussian shaping, peaking
time = t
p
)
4200 e鈥?rms at CD @ 500 pF, t
p
= 0.2 碌m
3200 e鈥?rms at CD @ 500 pF, t
p
= 1.0 碌m
4200 e鈥?rms at CD @ 500 pF, t
p
= 4.0 碌m
Bias 3
Packages & Test Circuit Overside
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287
FAX
(972) 276-3375
www.interfet.com
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